Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
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5.4.2.2. FPGA I/O Resources in Intel® Arria® 10 GT Packages

Table 35.  GPIO Buffers and LVDS Channels in Intel® Arria® 10 GT Devices
  • The SF45 package is a ball grid array with 1.0 mm pitch.
  • The number of LVDS channels does not include dedicated clock pins.
Product Line Package GPIO Buffers LVDS Channels
Code Type 3 V I/O LVDS I/O Total
GT 900 SF45 1,932-pin FBGA 0 624 624 312
GT 1150 SF45 1,932-pin FBGA 0 624 624 312