Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

5.7.4. Guideline: Using the I/O Pins in HPS Shared I/O Banks

In Intel® Arria® 10 SX devices, I/O banks 2K, 2J, and 2I connect the HPS to an SDRAM device through a dedicated HPS external memory interface.

Each of the I/O bank has four lanes:

  • Lane 3—IO[47..36]
  • Lane 2—IO[35..24]
  • Lane 1—IO[23..12]
  • Lane 0—IO[11..0]

If you do not include any HPS external memory interface in your system, you can use banks 2K, 2J, and 2I in the Intel® Arria® 10 SX device as FPGA GPIOs.

If you include an HPS external memory interface in your system, adhere to these guidelines if you want to use the unused pins in banks 2K, 2J, and 2I for FPGA GPIOs:

  • Bank 2K is used for SDRAM ECC, and address and command signals:
    • Lane 3 is used for SDRAM ECC signals. You can use the remaining pins in this lane for FPGA inputs only.
    • Lanes 2, 1, and 0 are used for SDRAM address and command signals. You can use the remaining pins in these lanes for FPGA inputs and outputs.
  • Bank 2J is used for SDRAM data signals [31..0] and bank 2I is used for SDRAM data signals [63..32].
    • 16 bits data width—two lanes of bank 2J is used for data. You can use the remaining pins in these two data lanes as FPGA inputs only. You can use the pins in the other two lanes of bank 2J, and all lanes of bank 2I as FPGA inputs or outputs.
    • 32 bits data width—you can use the remaining pins in all lanes of bank 2J as FPGA inputs only. You can use the pins in all lanes of bank 2I as FPGA inputs and outputs.
    • 64 bits data width—you can use the remaining pins in all lanes of banks 2J and 2I as FPGA inputs only.

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