Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 5/27/2022
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5.6.6.5. Guideline: Pin Placement for Differential Channels

Each I/O bank contains its own PLL. The I/O bank PLL can drive all receiver and transmitter channels in the same bank, and transmitter channels in adjacent I/O banks. However, the I/O bank PLL cannot drive receiver channels in another I/O bank or transmitter channels in non-adjacent I/O banks.

PLLs Driving Differential Transmitter Channels

For differential transmitters, the PLL can drive the differential transmitter channels in its own I/O bank and adjacent I/O banks. However, the PLL cannot drive the channels in a non-adjacent I/O bank.

The I/O bank PLL can drive the differential transmitter channels in an adjacent I/O bank only in a wide LVDS SERDES Intel® FPGA IP transmitter interface that spans multiple I/O banks, where:

  • With tx_outclock enabled—the transmitter has more than 22 channels
  • With tx_outclock disabled—the transmitter has more than 23 channels

For an LVDS SERDES Intel® FPGA IP transmitter interface contained within a single I/O bank, drive the transmitter using the PLL in the same I/O bank.

Figure 112. PLLs Driving Differential Transmitter Channels


PLLs Driving DPA-Enabled Differential Receiver Channels

For differential receivers, the PLL can drive only the channels within the same I/O bank.

Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel. If you enable a DPA channel in a bank, you can assign the unused I/O pins in the bank to single-ended or differential I/O standards that has the same VCCIO voltage level used by the bank.

DPA usage adds some constraints to the placement of high-speed differential receiver channels. The Intel® Quartus® Prime compiler automatically checks the design and issues error messages if there are placement guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.

Figure 113. PLLs Driving DPA-Enabled Differential Receiver Channels


PLLs Driving DPA-Enabled Differential Receiver and Transmitter Channels in LVDS Interface Spanning Multiple I/O Banks

If you use both differential transmitter and DPA-enabled receiver channels in a bank, the PLL can drive the transmitters spanning multiple adjacent I/O banks, but only the receivers in its own I/O bank.

Figure 114. PLLs Driving DPA-Enabled Differential Receiver and Transmitter Channels Across I/O Banks


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