Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

5.6.1. Intel® Arria® 10 LVDS SERDES Usage Modes

Table 60.  Usage Modes Summary of the Intel® Arria® 10 LVDS SERDESAll SERDES usage modes in this table support SERDES factors of 3 to 10.
Usage Mode Quick Guideline
Transmitter In this mode, the SERDES block acts as a serializer.
DPA Receiver
  • This mode is useful for source-synchronous clocking applications.
  • The dynamic phase alignment block (DPA) automatically adjusts the clock phase to achieve optimal data-to-clock skew.
Non-DPA Receiver
  • This mode is useful for source-synchronous clocking applications.
  • You must manage the data-to-clock skew.
Soft-CDR Receiver
  • The soft clock data recovery (soft-CDR) mode is useful for asynchronous clocking applications.
  • An asynchronous clock drives the LVDS SERDES IP core. The IP core outputs a recovered clock from the received data.
Bypass the SERDES

You can bypass the serializer to use SERDES factor of 2 by using the GPIO IP core:

  • Single data rate (SDR) mode—you do not require clocks.
  • Double data rate (DDR) mode—useful for slow source-synchronous clocking applications.

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