Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
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10.2.2. Programmable Power Technology

Intel® Arria® 10 devices offer the ability to configure portions of the core, called tiles, for high-speed or low-power mode of operation. This configuration is performed by the Intel® Quartus® Prime software automatically and without the need for user intervention. Setting a tile to high-speed or low-power mode is accomplished with on-chip circuitry and does not require extra power supplies. In a design compilation, the Intel® Quartus® Prime software determines whether a tile should be in high-speed or low-power mode based on the timing constraints of the design.

Intel® Arria® 10 tiles consist of the following:

  • Memory logic array block (MLAB)/ logic array block (LAB) pairs with routing to the pair
  • MLAB/LAB pairs with routing to the pair and to adjacent digital signal processing (DSP)/ memory block routing
  • TriMatrix memory blocks
  • DSP blocks

All blocks and routing associated with the tile share the same setting of either high-speed or low-power mode. By default, tiles that include DSP blocks or memory blocks are set to high-speed mode for optimum performance. Unused DSP blocks and memory blocks are set to low-power mode to minimize static power. Unused M20K blocks are set to sleep mode by disabling VCCERAM to reduce static power. Clock networks do not support programmable power technology.

With programmable power technology, faster speed grade FPGAs may require less static power compared with FPGA devices without programmable power technology. For device with programmable power technology, critical path is a small portion of the design. Therefore, there are fewer high-speed MLAB and LAB pairs in high-speed mode. For device without programmable power technology, the whole FPGA has to be over designed to meet the timing of the critical path.

The Intel® Quartus® Prime software sets unused device resources in the design to low-power mode to reduce the static power. It also sets the following resources to low-power mode when they are not used in the design:

  • LABs and MLABs
  • TriMatrix memory blocks
  • DSP blocks

If a phase-locked loop (PLL) is instantiated in the design, you may assert the areset pin high to keep the PLL in low-power mode.

Table 122.  Programmable Power Capabilities for Intel® Arria® 10 DevicesThis table lists the available Intel® Arria® 10 programmable power capabilities. Speed grade considerations can add to the permutations to give you flexibility in designing your system.
Feature Programmable Power Technology
LAB Yes
Routing Yes
Memory Blocks Fixed setting 48
DSP Blocks Fixed setting 48
Clock Networks No
48 Tiles with DSP blocks and memory blocks that are used in the design are always set to high-speed mode. By default, unused DSP blocks and memory blocks are set to low-power mode.