Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry

The IEEE Std. 1149.1 BST circuitry is enabled after the Intel® Arria® 10 device powers up. However for Intel® Arria® 10 SoC FPGAs, you must power up both HPS and FPGA to perform BST.

To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.

Table 120.  Pin Connections to Permanently Disable the IEEE Std. 1149.1 Circuitry for Intel® Arria® 10 Devices
JTAG Pins44 Connection for Disabling
TMS VCCPGM
TCK GND
TDI VCCPGM
TDO Leave open
TRST GND
44 The JTAG pins are dedicated. Software option is not available to disable JTAG in Intel® Arria® 10 devices.

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