9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
The IEEE Std. 1149.1 BST circuitry is enabled after the Intel® Arria® 10 device powers up. However for Intel® Arria® 10 SoC FPGAs, you must power up both HPS and FPGA to perform BST.
To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.
|JTAG Pins44||Connection for Disabling|