Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

2.7.1. Byte Enable Controls in Memory Blocks

Table 11.   byteena Controls in x20 Data Width
byteena[1:0] Data Bits Written
11 (default) [19:10] [9:0]
10 [19:10]
01 [9:0]
Table 12.   byteena Controls in x40 Data Width
byteena[3:0] Data Bits Written
1111 (default) [39:30] [29:20] [19:10] [9:0]
1000 [39:30]
0100 [29:20]
0010 [19:10]
0001 [9:0]

Did you find the information on this page useful?

Characters remaining:

Feedback Message