Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

5.4.1. GPIO Banks, SERDES, and DPA Locations in Intel® Arria® 10 Devices

The I/O banks are located in I/O columns. Each I/O bank contains its own PLL, DPA, and SERDES circuitries.

For more details about the I/O banks available in each device package, refer to the related information.

Figure 70. I/O Banks for Intel® Arria® 10 GX 160 and GX 220 Devices
Figure 71. I/O Banks for Intel® Arria® 10 SX 160 and SX 220 Devices
Figure 72. I/O Banks for Intel® Arria® 10 GX 270 and GX 320 Devices
Figure 73. I/O Banks for Intel® Arria® 10 SX 270 and SX 320 Devices
Figure 74. I/O Banks for Intel® Arria® 10 GX 480 Devices
Figure 75. I/O Banks for Intel® Arria® 10 SX 480 Devices
Figure 76. I/O Banks for Intel® Arria® 10 GX 570 and GX 660 Devices
Figure 77. I/O Banks for Intel® Arria® 10 SX 570 and SX 660 Devices
Figure 78. I/O Banks for Intel® Arria® 10 GX 900, GX 1150, GT 900, and GT 1150 Devices

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