9.6.1. Boundary-Scan Cells of an Intel® Arria® 10 Device I/O Pin
The Intel® Arria® 10 device 3-bit BSC consists of the following registers:
- Capture registers—Connect to internal device data through the OUTJ, OEJ, and PIN_IN signals.
- Update registers—Connect to external data through the PIN_OUT and PIN_OE signals.
The TAP controller generates the global control signals for the IEEE Std. 1149.1 BST registers (shift, clock, and update) internally. A decode of the instruction register generates the MODE signal.
The data signal path for the boundary-scan register runs from the serial data in (SDI) signal to the serial data out (SDO) signal. The scan register begins at the TDI pin and ends at the TDO pin of the device.
|Output Capture Register||OE Capture Register||Input Capture Register||Output Update Register||OE Update Register||Input Update Register|
|User I/O pins||OUTJ||OEJ||PIN_IN||PIN_OUT||PIN_OE||INJ||—|
|Dedicated clock input||No Connect (N.C.)||N.C.||PIN_IN||N.C.||N.C.||N.C.||PIN_IN drives to the clock network or logic array|
|Dedicated input||N.C.||N.C.||PIN_IN||N.C.||N.C.||N.C.||PIN_IN drives to the control logic|
|Dedicated bidirectional (open drain)45||0||OEJ||PIN_IN||N.C.||N.C.||N.C.||PIN_IN drives to the configuration control|
|Dedicated bidirectional46||OUTJ||OEJ||PIN_IN||N.C.||N.C.||N.C.||PIN_IN drives to the configuration control and OUTJ drives to the output buffer|
|Dedicated output47||OUTJ||0||0||N.C.||N.C.||N.C.||OUTJ drives to the output buffer|