Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents

10.2.4. SmartVID Feature Implementation

The implementation of the SmartVID feature consists of 7-bit voltage identification (VID) that is programmed into a fuse block during device manufacturing.

The 7-bit VID represents a voltage level in the range of 0.85 V to 0.9 V. Each device has its own specific 7-bit VID. You can read the 7-bit VID using the SmartVID Controller IP core. You have the option to enable or disable the VID bit reading.

The 7-bit VID is read from the fuse block and sent to the external regulator or system power controller through the Intel FPGA-supported interface. Upon receiving the 7-bit VID value, an adjustable regulator tunes down the VCC and VCCP voltage levels to a lower voltage as specified by the 7-bit VID. Multiple interface methods are supported for the Arria® 10 device to communicate the VID value to an external regulator or system power controller. The first method to be available is the 7-bit parallel interface.

Intel offers external regulators and system power controllers that support the SmartVID feature and are compatible with the multiple interfaces methods utilized by the Arria® 10 device.

The 7-Bit Parallel Interface Solution

The 7-bit parallel solution is a parallel VID bit interface that is supported by Intel® . This interface requires seven I/O pins for seven parallel VID bits and one pin for the VID_EN to communicate with the external regulator.

Intel® recommends you to use the RZQ_2A pin for the VID_EN function. If bank 2A is used for DDR interface, and the RZQ_2A pin must be used for calibration purpose, you can use other available general-purpose I/O pins for the VID_EN pin function. Before the VID_EN pin is asserted, you need to ensure the I/O bank that hosts the VID_EN pin and VID pins are powered up. Connect the VID_EN pin to a 1-kΩ pull-down resistor.

The VID pins need to be tri-stated during power-up and before the VID_EN pin is asserted. Intel® recommends using a level shifter to isolate the VID signals and voltage regulator controller. This is because some of the VID bit settings may exceed the maximum VCC and VCCP values.

Figure 181. External Interface Connection for the 7-Bit Parallel Solution

The following table lists the regulator requirement to meet the Intel® SmartVID solution.

Table 124.  Regulator Requirement for Intel® SmartVID Solution
Specification Value
Voltage range 0.82 V – 0.93 V 49
Voltage step 10 mV step
VCC power supply 10 W – 100 W
VID input 7-bit VID
Nominal voltage 0.85 V – 0.9 V 50
Ramp time 0.5 mV/us
VID_EN pin 1 pin
49 This voltage range is the output of the regulator to the Arria® 10 device, inclusive of tolerance.
50 The nominal device power-up voltage is 0.9 V.