Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

3.3. Design Considerations

You should consider the following elements in your design:

Table 18.  Design Considerations
DSP Implementation Fixed-Point Arithmetic Floating-Point Arithmetic
Design elements
  • Operational modes
  • Internal coefficient and pre-adder
  • Accumulator
  • Chainout adder
  • Operational modes
  • Chainout adder
The Intel® Quartus® Prime software provides the following design templates for you to implement DSP blocks in Intel® Arria® 10 devices.
Table 19.  DSP Design Templates Available in Intel® Arria® 10 Devices
Operational Mode Available Design Templates
18 x 18 Independent Multiplier Mode Single Multiplier with Preadder and Coefficient
27 x 27 Independent Multiplier Mode
  • M27x27 with Dynamic Negate
  • M27x27 with Preadder and Coefficient
  • M27x27 with Input Cascade, Output Chaining, Accumulator, Double Accumulator, and Preload Constant
Multiplier Adder Sum Mode
  • M18x19_sumof2 with Dynamic Sub and Dynamic Negate
  • M18x19_sumof2 with Preadder and Coefficient
  • M18x19_sumof2 with Input Cascade, Output Chaining, Accumulator, Double Accumulator, and Preload Constant
18 x 19 Multiplication Summed with 36-Bit Input Mode
  • M18x19_plus36 with Dynamic Sub and Dynamic Negate
  • M18x19_plus36 with Input Cascade, Output Chaining, Accumulator, Double Accumulator, and Preload Constant
18-bit Systolic FIR Mode
  • M18x19_systolic with Preadder and Coefficient
  • M18x19_systolic with Input Cascade, Output Chaining, Accumulator, Double Accumulator, and Preload Constant
You can get the design templates using the following steps:
  1. In Intel® Quartus® Prime software, open a new Verilog HDL or VHDL file.
  2. From Edit tab, click Insert Template.
  3. From the Insert Template window prompt, you may select Verilog HDL or VHDL depending on your preferred design language.
  4. Click Full Designs to expand the options.
  5. From the options, click Arithmetic > DSP Features > > DSP Features for 20-nm Device.
  6. Choose the design template that match your system requirement and click Insert to append the design template to a new .v or .vhd file.

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