Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

5.4.2.3. FPGA I/O Resources in Intel® Arria® 10 SX Packages

Table 36.  GPIO Buffers and LVDS Channels in Intel® Arria® 10 SX Devices
  • The U19 package is a ball grid array with 0.8 mm pitch. All other packages are ball grid arrays with 1.0 mm pitch.
  • The number of LVDS channels does not include dedicated clock pins.
Product Line Package GPIO Buffers LVDS Channels
Code Type 3 V I/O LVDS I/O Total
SX 160 U19 484-pin UBGA 48 148 196 74
F27 672-pin FBGA 48 192 240 96
F29 780-pin FBGA 48 240 288 120
SX 220 U19 484-pin UBGA 48 148 196 74
F27 672-pin FBGA 48 192 240 96
F29 780-pin FBGA 48 240 288 120
SX 270 F27 672-pin FBGA 48 192 240 96
F29 780-pin FBGA 48 312 360 156
F34 1,152-pin FBGA 48 336 384 168
F35 1,152-pin FBGA 48 336 384 168
SX 320 F27 672-pin FBGA 48 192 240 96
F29 780-pin FBGA 48 312 360 156
F34 1,152-pin FBGA 48 336 384 168
F35 1,152-pin FBGA 48 336 384 168
SX 480 F29 780-pin FBGA 48 312 360 156
F34 1,152-pin FBGA 48 444 492 222
F35 1,152-pin FBGA 48 348 396 174
SX 570 F34 1,152-pin FBGA 48 444 492 222
F35 1,152-pin FBGA 48 348 396 174
NF40 1,517-pin FBGA 48 540 588 270
KF40 1,517-pin FBGA 96 600 696 300
SX 660 F34 1,152-pin FBGA 48 444 492 222
F35 1,152-pin FBGA 48 348 396 174
NF40 1,517-pin FBGA 48 540 588 270
KF40 1,517-pin FBGA 96 600 696 300

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