Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

4.1.5.4. PCLK Control Block

PCLK control block drives both SPCLK and LPCLK networks.

To drive the HSSI PCLK, select the HSSI output, fPLL output, or clock input pin.

To drive the I/O PCLK, select the DPA clock output, I/O PLL output, or clock input pin.

Figure 59. PCLK Control Block for HSSI Column for Intel® Arria® 10 Devices


Figure 60. PCLK Control Block for I/O Column for Intel® Arria® 10 Devices


You can set the input clock sources and the clkena signals for the PCLK networks through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.

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