22.214.171.124. PCLK Control Block
PCLK control block drives both SPCLK and LPCLK networks.
To drive the HSSI PCLK, select the HSSI output, fPLL output, or clock input pin.
To drive the I/O PCLK, select the DPA clock output, I/O PLL output, or clock input pin.
You can set the input clock sources and the clkena signals for the PCLK networks through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.