Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

5.6.7.1.4. Receiver Skew Margin for Non-DPA Mode

Different modes of LVDS receivers use different specifications, which can help in deciding the ability to sample the received serial data correctly.
  • In DPA mode, use DPA jitter tolerance instead of the receiver skew margin (RSKM).
  • In non-DPA mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed source-synchronous differential signals in the receiver data path.

RSKM Equation

The RSKM equation expresses the relationship between RSKM, TCCS, and SW.
Figure 122. RSKM Equation


Conventions used for the equation:

  • RSKM—the timing margin between the clock input of the receiver and the data input sampling window, and the jitter induced from core noise and I/O switching noise.
  • Time unit interval (TUI)—time period of the serial data.
  • SW—the period of time that the input data must be stable to ensure that the LVDS receiver samples the data successfully. The SW is a device property and varies according to device speed grade.
  • TCCS—the timing difference between the fastest and the slowest output edges across channels driven by the same PLL. The TCCS measurement includes the tCO variation, clock, and clock skew.
Note: If there is additional board channel-to-channel skew, consider the total receiver channel-to-channel skew (RCCS) instead of TCCS. .

You must calculate the RSKM value, based on the data rate and device, to determine if the LVDS receiver can sample the data:

  • A positive RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver can sample the data properly.
  • A negative RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver cannot sample the data properly.
Figure 123. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode This figure shows the relationship between the RSKM, TCCS, and the SW of the receiver.


RSKM Report for LVDS Receiver

For LVDS receivers, the Intel® Quartus® Prime software provides an RSKM report showing the SW, TUI, and RSKM values for the non-DPA LVDS mode.
  • To generate the RSKM report, run the report_RSKM command in the TimeQuest Timing Analyzer. The RSKM report is available in the TimeQuest Timing Analyzer section of the Intel® Quartus® Prime compilation report.
  • To obtain a more realistic RSKM value, assign the input delay to the LVDS receiver through the constraints menu of the TimeQuest Timing Analyzer. The input delay is determined according to the data arrival time at the LVDS receiver port, with respect to the reference clock.
  • If you set the input delay in the settings parameters for the Set Input Delay option, set the clock name to the clock that references the source-synchronous clock that feeds the LVDS receiver.
  • If you do not set any input delay in the TimeQuest Timing Analyzer, the receiver channel-to-channel skew defaults to zero.
  • You can also directly set the input delay in a Synopsys Design Constraint file (.sdc) by using the set_input_delay command.

Example: RSKM Calculation

This example shows the RSKM calculation for FPGA devices at 1 Gbps data rate with a 200 ps board channel-to-channel skew.
  • TCCS = 150 ps
  • SW = 300 ps
  • TUI = 1000 ps
  • Total RCCS = TCCS + Board channel-to-channel skew = 150 ps + 200 ps = 350 ps
  • RSKM = (TUI – SW – RCCS) / 2 = (1000 ps – 300 ps – 350 ps) / 2 = 175 ps

If the RSKM is greater than 0 ps after deducting transmitter jitter, the non-DPA receiver will work correctly.

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