Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
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4.2.4. Clock Feedback Modes

Clock feedback modes compensate for clock network delays to align the PLL clock input rising edge with the rising edge of the clock output. Select the appropriate type of compensation for the timing critical clock path in your design.

PLL compensation is not always needed. A PLL should be configured in direct (no compensation) mode unless a need for compensation is identified. Direct mode provides the best PLL jitter performance and avoids expending compensation clocking resources unnecessarily.

The default clock feedback mode is direct compensation mode.

fPLLs support the following clock feedback modes:

  • Direct compensation
  • Feedback compensation bonding

I/O PLLs support the following clock feedback modes:

  • Direct compensation
  • Normal compensation
  • Source synchronous compensation
  • LVDS compensation
  • Zero delay buffer (ZDB) compensation
  • External feedback (EFB) compensation