Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents Programmable IOE Delay

You can activate the programmable IOE delays to ensure zero hold time, minimize setup time, or increase clock-to-output time. This feature helps read and write timing margins because it minimizes the uncertainties between signals in the bus.

To ensure that the signals within a bus have the same delay going into or out of the device, each pin can have different delay values:

  • Delay from input pin to input register
  • Delay from output pin to output register
  • In the output and OE paths, there are the output and OE delays which have 50 ps incremental delays and a maximum delay of 800 ps.
  • In the input paths, there are two input delay chains with incremental delays of 50 ps and a maximum delay of 3.2 ns.

For more information about the programmable IOE delay specifications, refer to the device datasheet.