Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

7.2.2. Passive Serial Configuration

Figure 139. High-Level Overview of Flash Programming for PS Configuration Scheme


The PS configuration scheme uses an external host. You can use a microprocessor, MAX II device, MAX V device, or a host PC as the external host.

You can use an external host to control the transfer of configuration data from an external storage such as flash memory to the FPGA. The design that controls the configuration process resides in the external host.

You can store the configuration data in Programmer Object File (.pof), .rbf , .hex , or .ttf . If you are using configuration data in .rbf , .hex , or .ttf , send the LSB of each data byte first. For example, if the .rbf contains the byte sequence 02 1B EE 01 FA, the serial data transmitted to the device must be 0100-0000 1101-1000 0111-0111 1000-0000 0101-1111.

You can use the PFL IP core with a MAX II or MAX V device to read configuration data from the flash memory device and configure the Intel® Arria® 10 device.

For a PC host, connect the PC to the device using an Intel FPGA download cable.

The configuration data is shifted serially into the DATA0 pin of the device.

If you are using the Intel® Quartus® Prime programmer and the CLKUSR pin is enabled, you do not need to provide a clock source for the pin to initialize your device.

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