Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents

4.2. Arria® 10 PLLs

PLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Arria® 10 device family contains the following PLLs:

  • fPLLs—can function as fractional PLLs or integer PLLs
  • I/O PLLs—can only function as integer PLLs

The fPLLs are located adjacent to the transceiver blocks in the HSSI banks. Each HSSI bank contains two fPLLs. You can configure each fPLL independently in conventional integer mode or fractional mode. In fractional mode, the fPLL can operate with third-order delta-sigma modulation. Each fPLL has four C counter outputs and one L counter output.

The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. Each I/O bank contains one I/O PLL. The I/O PLLs can operate in conventional integer mode. Each I/O PLL has nine C counter outputs. In some specific device package, you can use the I/O PLLs in the I/O banks that are not bonded out in your design. These I/O PLLs must take their reference clock source from the FPGA core or through a dedicated cascade connection from another I/O PLL in the same I/O column.

Arria® 10 devices have up to 32 fPLLs and 16 I/O PLLs in the largest densities. Arria® 10 PLLs have different core analog structure and features support.

Table 30.  PLL Features in Arria® 10 Devices
Feature Fractional PLL I/O PLL
Integer mode Yes Yes
Fractional mode Yes
C output counters 4 9
M counter divide factors 8 to 127 4 to 160
N counter divide factors 1 to 32 1 to 80
C counter divide factors 1 to 512 1 to 512
L counter divide factors 1, 2, 4, 8
Dedicated external clock outputs Yes
Dedicated clock input pins Yes Yes
External feedback input pin Yes
Spread-spectrum input clock tracking 4 Yes Yes
Source synchronous compensation Yes
Direct compensation Yes Yes
Normal compensation Yes
Zero-delay buffer compensation Yes
External feedback compensation Yes
LVDS compensation Yes
Feedback compensation bonding Yes
Voltage-controlled oscillator (VCO) output drives the DPA clock Yes
Phase shift resolution 5 72 ps 78.125 ps
Programmable duty cycle Fixed 50% duty cycle Yes
Power down mode Yes Yes
4 Provided input clock jitter is within input jitter tolerance specifications.
5 The smallest phase shift is determined by the VCO period divided by four (for fPLL) or eight (for I/O PLL). For degree increments, the Arria® 10 device can shift all output frequencies in increments of at least 45° (for I/O PLL) or 90° (for fPLL). Smaller degree increments are possible depending on the frequency and divide parameters.