4.2. Intel® Arria® 10 PLLs
PLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.
The Intel® Arria® 10 device family contains the following PLLs:
- fPLLs—can function as fractional PLLs or integer PLLs
- I/O PLLs—can only function as integer PLLs
The fPLLs are located adjacent to the transceiver blocks in the HSSI banks. Each HSSI bank contains two fPLLs. You can configure each fPLL independently in conventional integer mode or fractional mode. In fractional mode, the fPLL can operate with third-order delta-sigma modulation. Each fPLL has four C counter outputs and one L counter output.
The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. Each I/O bank contains one I/O PLL. The I/O PLLs can operate in conventional integer mode. Each I/O PLL has nine C counter outputs. In some specific device package, you can use the I/O PLLs in the I/O banks that are not bonded out in your design. These I/O PLLs must take their reference clock source from the FPGA core or through a dedicated cascade connection from another I/O PLL in the same I/O column.
Intel® Arria® 10 devices have up to 32 fPLLs and 16 I/O PLLs in the largest densities. Intel® Arria® 10 PLLs have different core analog structure and features support.
|Feature||Fractional PLL||I/O PLL|
|C output counters||4||9|
|M counter divide factors||8 to 127||4 to 160|
|N counter divide factors||1 to 32||1 to 80|
|C counter divide factors||1 to 512||1 to 512|
|L counter divide factors||1, 2, 4, 8||—|
|Dedicated external clock outputs||—||Yes|
|Dedicated clock input pins||Yes||Yes|
|External feedback input pin||—||Yes|
|Spread-spectrum input clock tracking 4||Yes||Yes|
|Source synchronous compensation||—||Yes|
|Zero-delay buffer compensation||—||Yes|
|External feedback compensation||—||Yes|
|Feedback compensation bonding||Yes||—|
|Voltage-controlled oscillator (VCO) output drives the DPA clock||—||Yes|
|Phase shift resolution 5||72 ps||78.125 ps|
|Programmable duty cycle||Fixed 50% duty cycle||Yes|
|Power down mode||Yes||Yes|
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