Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
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4.2.1. PLL Usage

fPLLs are optimized for use as transceiver transmit PLLs and for synthesizing reference clock frequencies. You can use the fPLLs as follows:

  • Reduce the number of required oscillators on the board
  • Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source
  • Compensate clock network delay
  • Transmit clocking for transceivers

I/O PLLs are optimized for use with memory interfaces and LVDS SERDES. You can use the I/O PLLs as follows:

  • Reduce the number of required oscillators on the board
  • Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source
  • Simplify the design of external memory interfaces and high-speed LVDS interfaces
  • Ease timing closure because the I/O PLLs are tightly coupled with the I/Os
  • Compensate clock network delay
  • Zero delay buffering