Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
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6.5.3. Intel® Arria® 10 Package Support for DDR4 x40 with ECC

To support one DDR4 x40 interface with ECC (32 bits data + 8 bits ECC), you require two I/O banks.

Table 79.  Number of DDR4 x40 Interfaces (with ECC) Supported Per Device Package (without HPS Instance)
Product Line Package
U19 F27 F29 F34 F35 NF40 KF40 RF40 NF45 SF45 UF45
GX 160 1 1 2
GX 220 1 1 2
GX 270 1 2 3 3
GX 320 1 2 3 3
GX 480 2 4 3
GX 570 4 3 5 5
GX 660 4 3 5 5
GX 900 4 5 1 7 6 4
GX 1150 4 5 1 7 6 4
GT 900 6
GT 1150 7 6
SX 160 1 19 1 19 2 19
SX 220 1 19 1 19 2 19
SX 270 1 19 2 19 3 19 3
SX 320 1 19 2 19 3 19 3 19
SX 480 2 419 3 19
SX 570 4 19 3 19 5 19 6 20 19
SX 660 4 19 3 19 5 19 620 19
Table 80.  Number of DDR4 x40 Interfaces (with ECC) Supported Per Device Package (with HPS Instance)The number of supported interfaces shown in this table excludes the interface used to connect the HPS to external SDRAM. Masters in the FPGA core can access the HPS-connected external memory interface via FPGA-to-SDRAM bridge ports configurable in the HPS.
Product Line Package
U19 F27 F29 F34 F35 NF40 KF40 RF40 NF45 SF45 UF45
SX 160 0 0 1
SX 220 0 0 1
SX 270 0 1 2 2
SX 320 0 1 2 2
SX 480 1 3 2
SX 570 3 2 4 4
SX 660 3 2 4 4
19 This number includes HPS shared I/O banks to implement core EMIF configurations.
20 This number includes using the 3 V I/O bank for external memory interfaces. Otherwise, the number of external memory interfaces possible is reduced by one.