Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

6.7.2. I/O AUX

There is one I/O AUX block in each I/O column:

  • Contains a hard Nios® II processor and supporting embedded memory block
  • Handles the calibration algorithm for the entire I/O column
  • Communicates to the sequencer in each I/O bank through a dedicated Avalon® interface
Figure 131. IO AUX Block Diagram


The hard Nios® II processor performs the following operations:

  • Configures and starts calibration tasks on the sequencers
  • Collects and processes data
  • Uses the final results to configure the I/Os

A combination of both Nios® II code and the sequencers, the algorithm implementation supports calibration for the following memory interface standards:

  • DDR2, DDR3, and DDR4 SDRAM
  • QDR II and QDR IV SRAM
  • RLDRAM 3
  • LPDDR2 and LPDDR3
Note: Intel recommends that you use the Nios® subsystem for memory interface calibration.

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