Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

6.7.1.5. I/O Lane

There are four I/O lanes in each I/O bank. Each I/O lane contains 12 I/O pins with identical read and write data paths and buffers.

Figure 130.  I/O Lane Architecture


Data Path Component Description

Input path

Contains capture registers and read FIFO.

Output or output enable (oe) path

Consists of:

  • Write FIFO
  • Clock mux
  • Phase interpolater— supports around 5 to 10 ps resolution based on frequency
  • Double data rate control
Input delay chain

Supports around 5 ps resolution with a delay range of 0 to 625 ps.

Read/write buffer

The write data buffer has built in options to take data from the core or from the hard memory controller.

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