Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

4.1.5.3. RCLK Control Block

You can only control the clock source selection for the RCLK select block statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Intel® Quartus® Prime software.

Figure 58. RCLK Control Block for Intel® Arria® 10 Devices


You can set the input clock sources and the clkena signals for the RCLK networks through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.

Did you find the information on this page useful?

Characters remaining:

Feedback Message