188.8.131.52. RCLK Control Block
You can only control the clock source selection for the RCLK select block statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Intel® Quartus® Prime software.
You can set the input clock sources and the clkena signals for the RCLK networks through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.
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