Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents RCLK Control Block

You can only control the clock source selection for the RCLK select block statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Quartus® Prime software.

Figure 58. RCLK Control Block for Arria® 10 Devices

You can set the input clock sources and the clkena signals for the RCLK networks through the Quartus® Prime software using the ALTCLKCTRL IP core.