Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Document Table of Contents

3.3.5. DSP Block Cascade Limit in Intel® Arria® 10 Devices

The spine clock region limits the number of DSP blocks cascade. For Intel® Arria® 10 devices, you can cascade up to 27 DSP blocks.

Did you find the information on this page useful?

Characters remaining:

Feedback Message