Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents

7.4.5. Remote System Upgrade Registers

Table 101.  Remote System Upgrade Registers
Register Description

This register is accessible by the core logic and allows the update, status, and control registers to be written and sampled by user logic.


This register contains the current page address, watchdog timer settings, and one bit specifying the current configuration image—factory configuration or application configuration image. This register is used by the AS controller to load the configuration image from the EPCQ-L device during remote system upgrade.


This register contains similar data as the control register, but this register is updated by the factory configuration or application configuration image by shifting data into the shift register, followed by an update. The soft IP core of the remote system upgrade updates this register with the values to be used in the control register during the next reconfiguration cycle.


This register is written by the remote update block during every reconfiguration cycle to record the trigger of a reconfiguration. This information is used by the soft IP core of the remote system upgrade to determine the appropriate action following a reconfiguration cycle.