Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

3.4.2. Pipeline Register

Pipeline register is used to get the maximum Fmax performance. Pipeline register can be bypassed if high Fmax is not needed.

The following variable precision DSP block signals control the pipeline registers within the variable precision DSP block:
  • CLK[2..0]
  • ENA[2..0]
  • ACLR[1]
Floating-point arithmetic has 2 latency layers of pipeline registers where you can perform one of the following:
  • Bypass all latency layers of pipeline registers
  • Use either one latency layers of pipeline registers
  • Use both latency layers of pipeline registers

Did you find the information on this page useful?

Characters remaining:

Feedback Message