Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

2.2.1. Consider the Memory Block Selection

The Intel® Quartus® Prime software automatically partitions the user-defined memory into the memory blocks based on your design's speed and size constraints. For example, the Intel® Quartus® Prime software may spread out the memory across multiple available memory blocks to increase the performance of the design.

To assign the memory to a specific block size manually, use the RAM IP core in the parameter editor.

For the MLABs, you can implement single-port SRAM through emulation using the Intel® Quartus® Prime software. Emulation results in minimal additional use of logic resources.

Because of the dual purpose architecture of the MLAB, only data input registers, output registers, and write address registers are available in the block. The MLABs gain read address registers from the ALMs.

Note: For Intel® Arria® 10 devices, the Resource Property Editor and the Timing Analyzer report the location of the M20K block as EC_X<number>_Y<number>_N<number>, although the allowed assigned location is M20K_ X<number>_Y<number>_N<number>. Embedded Cell (EC) is the sublocation of the M20K block.

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