Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents Voltage-Referenced I/O Standards

To accommodate voltage-referenced I/O standards:

  • Each Arria® 10 FPGA I/O bank contains a dedicated VREF pin.
  • Each bank can have only a single VCCIO voltage level and a single voltage reference (VREF) level.

The voltage-referenced input buffer is powered by VCCPT. Therefore, an I/O bank featuring single-ended or differential standards can support different voltage-referenced standards under the following conditions:

  • The VREF are the same levels.
  • On-chip parallel termination (RT OCT) is disabled.

If you enable RT OCT, the voltage for the input standard and the VCCIO of the bank must match.

This feature allows you to place voltage-referenced input signals in an I/O bank with a VCCIO of 2.5 V or below. For example, you can place HSTL-15 input pins in an I/O bank with 2.5 V VCCIO. However, the voltage-referenced input with RT OCT enabled requires the VCCIO of the I/O bank to match the voltage of the input standard. RT OCT cannot be supported for the HSTL-15 I/O standard when VCCIO is 2.5 V.