Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Document Table of Contents

8.4.1. Error Detection Frequency

When you are unable to unload the EMR within the EMR update interval specification, you can reduce the error detection frequency. You can control the speed of the error detection process by setting the division factor of the clock frequency in the Intel® Quartus® Prime software.

Note: There is no significant power benefited from reducing the error detection frequency.

The speed of the error detection process for each data frame is determined by the following equation:

Figure 175. Error Detection Frequency Equation

Table 112.  Error Detection Frequency Range for Intel® Arria® 10 DevicesThe following table lists the FMIN and FMAX for each speed grade.
Note: Frequencies shown are when N = 1. For N = 2 or 4, divide the frequency shown accordingly.
Speed Grade Error Detection Frequency
1 49 77
2 45 77
3 42 77

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