Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

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ID 683461
Date 10/25/2023
Public
Document Table of Contents
Document Table of Contents x
1. Logic Array Blocks and Adaptive Logic Modules in Intel® Arria® 10 Devices 2. Embedded Memory Blocks in Intel® Arria® 10 Devices 3. Variable Precision DSP Blocks in Intel® Arria® 10 Devices 4. Clock Networks and PLLs in Intel® Arria® 10 Devices 5. I/O and High Speed I/O in Intel® Arria® 10 Devices 6. External Memory Interfaces in Intel® Arria® 10 Devices 7. Configuration, Design Security, and Remote System Upgrades in Intel® Arria® 10 Devices 8. SEU Mitigation for Intel® Arria® 10 Devices 9. JTAG Boundary-Scan Testing in Intel® Arria® 10 Devices 10. Power Management in Intel® Arria® 10 Devices
1. Logic Array Blocks and Adaptive Logic Modules in Intel® Arria® 10 Devices x
1.1. LAB 1.2. ALM Operating Modes 1.3. LAB Power Management Techniques 1.4. Logic Array Blocks and Adaptive Logic Modules in Intel® Arria® 10 Devices Revision History
1.1. LAB x
1.1.1. MLAB 1.1.2. Local and Direct Link Interconnects 1.1.3. Shared Arithmetic Chain and Carry Chain Interconnects 1.1.4. LAB Control Signals 1.1.5. ALM Resources 1.1.6. ALM Output
1.2. ALM Operating Modes x
1.2.1. Normal Mode 1.2.2. Extended LUT Mode 1.2.3. Arithmetic Mode 1.2.4. Shared Arithmetic Mode
2. Embedded Memory Blocks in Intel® Arria® 10 Devices x
2.1. Types of Embedded Memory 2.2. Embedded Memory Design Guidelines for Intel® Arria® 10 Devices 2.3. Embedded Memory Features 2.4. Embedded Memory Modes 2.5. Embedded Memory Clocking Modes 2.6. Parity Bit in Embedded Memory Blocks 2.7. Byte Enable in Embedded Memory Blocks 2.8. Memory Blocks Packed Mode Support 2.9. Memory Blocks Address Clock Enable Support 2.10. Memory Blocks Asynchronous Clear 2.11. Memory Blocks Error Correction Code Support 2.12. Embedded Memory Blocks in Intel® Arria® 10 Devices Revision History
2.1. Types of Embedded Memory x
2.1.1. Embedded Memory Capacity in Intel® Arria® 10 Devices
2.2. Embedded Memory Design Guidelines for Intel® Arria® 10 Devices x
2.2.1. Consider the Memory Block Selection 2.2.2. Guideline: Implement External Conflict Resolution 2.2.3. Guideline: Customize Read-During-Write Behavior 2.2.4. Guideline: Consider Power-Up State and Memory Initialization 2.2.5. Guideline: Control Clocking to Reduce Power Consumption
2.2.3. Guideline: Customize Read-During-Write Behavior x
2.2.3.1. Same-Port Read-During-Write Mode 2.2.3.2. Mixed-Port Read-During-Write Mode
2.4. Embedded Memory Modes x
2.4.1. Embedded Memory Configurations for Single-port Mode 2.4.2. Embedded Memory Configurations for Dual-port Modes
2.5. Embedded Memory Clocking Modes x
2.5.1. Clocking Modes for Each Memory Mode 2.5.2. Asynchronous Clears in Clocking Modes 2.5.3. Output Read Data in Simultaneous Read/Write 2.5.4. Independent Clock Enables in Clocking Modes
2.5.1. Clocking Modes for Each Memory Mode x
2.5.1.1. Single Clock Mode 2.5.1.2. Read/Write Clock Mode 2.5.1.3. Input/Output Clock Mode 2.5.1.4. Independent Clock Mode
2.7. Byte Enable in Embedded Memory Blocks x
2.7.1. Byte Enable Controls in Memory Blocks 2.7.2. Data Byte Output 2.7.3. RAM Blocks Operations
2.11. Memory Blocks Error Correction Code Support x
2.11.1. Error Correction Code Truth Table
3. Variable Precision DSP Blocks in Intel® Arria® 10 Devices x
3.1. Supported Operational Modes in Intel® Arria® 10 Devices 3.2. Resources 3.3. Design Considerations 3.4. Block Architecture 3.5. Operational Mode Descriptions 3.6. Variable Precision DSP Blocks in Intel® Arria® 10 Devices Revision History
3.1. Supported Operational Modes in Intel® Arria® 10 Devices x
3.1.1. Features
3.3. Design Considerations x
3.3.1. Operational Modes 3.3.2. Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic 3.3.3. Accumulator for Fixed-Point Arithmetic 3.3.4. Chainout Adder 3.3.5. DSP Block Cascade Limit in Intel Agilex® 7 Devices
3.4. Block Architecture x
3.4.1. Input Register Bank 3.4.2. Pipeline Register 3.4.3. Pre-Adder for Fixed-Point Arithmetic 3.4.4. Internal Coefficient for Fixed-Point Arithmetic 3.4.5. Multipliers 3.4.6. Adder 3.4.7. Accumulator and Chainout Adder for Fixed-Point Arithmetic 3.4.8. Systolic Registers for Fixed-Point Arithmetic 3.4.9. Double Accumulation Register for Fixed-Point Arithmetic 3.4.10. Output Register Bank
3.4.1. Input Register Bank x
3.4.1.1. Two Sets of Delay Registers for Fixed-Point Arithmetic
3.5. Operational Mode Descriptions x
3.5.1. Operational Modes for Fixed-Point Arithmetic 3.5.2. Operational Modes for Floating-Point Arithmetic
3.5.1. Operational Modes for Fixed-Point Arithmetic x
3.5.1.1. Independent Multiplier Mode 3.5.1.2. Independent Complex Multiplier 3.5.1.3. Multiplier Adder Sum Mode 3.5.1.4. 18 x 19 Multiplication Summed with 36-Bit Input Mode 3.5.1.5. Systolic FIR Mode
3.5.1.1. Independent Multiplier Mode x
3.5.1.1.1. 18 x 18 or 18 x 19 Independent Multiplier 3.5.1.1.2. 27 x 27 Independent Multiplier
3.5.1.2. Independent Complex Multiplier x
3.5.1.2.1. 18 x 19 Complex Multiplier
3.5.1.5. Systolic FIR Mode x
3.5.1.5.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.5.1.5.2. 18-Bit Systolic FIR Mode 3.5.1.5.3. 27-Bit Systolic FIR Mode
3.5.2. Operational Modes for Floating-Point Arithmetic x
3.5.2.1. Single Floating-Point Arithmetic Functions 3.5.2.2. Multiple Floating-Point Arithmetic Functions
3.5.2.1. Single Floating-Point Arithmetic Functions x
3.5.2.1.1. Multiplication Mode 3.5.2.1.2. Adder or Subtract Mode 3.5.2.1.3. Multiply Accumulate Mode
3.5.2.2. Multiple Floating-Point Arithmetic Functions x
3.5.2.2.1. Multiply-Add or Multiply-Subtract Mode 3.5.2.2.2. Vector One Mode 3.5.2.2.3. Vector Two Mode 3.5.2.2.4. Direct Vector Dot Product 3.5.2.2.5. Complex Multiplication
4. Clock Networks and PLLs in Intel® Arria® 10 Devices x
4.1. Clock Networks 4.2. Intel® Arria® 10 PLLs 4.3. Clock Networks and PLLs in Intel® Arria® 10 Devices Revision History
4.1. Clock Networks x
4.1.1. Clock Resources in Intel® Arria® 10 Devices 4.1.2. Hierarchical Clock Networks 4.1.3. Types of Clock Networks 4.1.4. Clock Network Sources 4.1.5. Clock Control Block 4.1.6. Clock Power Down 4.1.7. Clock Enable Signals
4.1.3. Types of Clock Networks x
4.1.3.1. Global Clock Networks 4.1.3.2. Regional Clock Networks 4.1.3.3. Periphery Clock Networks
4.1.4. Clock Network Sources x
4.1.4.1. Dedicated Clock Input Pins 4.1.4.2. Internal Logic 4.1.4.3. DPA Outputs 4.1.4.4. HSSI Clock Outputs 4.1.4.5. PLL Clock Outputs
4.1.5. Clock Control Block x
4.1.5.1. Pin Mapping in Intel® Arria® 10 Devices 4.1.5.2. GCLK Control Block 4.1.5.3. RCLK Control Block 4.1.5.4. PCLK Control Block
4.2. Intel® Arria® 10 PLLs x
4.2.1. PLL Usage 4.2.2. PLL Architecture 4.2.3. PLL Control Signals 4.2.4. Clock Feedback Modes 4.2.5. Clock Multiplication and Division 4.2.6. Programmable Phase Shift 4.2.7. Programmable Duty Cycle 4.2.8. PLL Cascading 4.2.9. Reference Clock Sources 4.2.10. Clock Switchover 4.2.11. PLL Reconfiguration and Dynamic Phase Shift
4.2.3. PLL Control Signals x
4.2.3.1. Reset 4.2.3.2. Locked
4.2.10. Clock Switchover x
4.2.10.1. Automatic Switchover 4.2.10.2. Automatic Switchover with Manual Override 4.2.10.3. Manual Clock Switchover 4.2.10.4. Guidelines
5. I/O and High Speed I/O in Intel® Arria® 10 Devices x
5.1. I/O and Differential I/O Buffers in Intel® Arria® 10 Devices 5.2. I/O Standards and Voltage Levels in Intel® Arria® 10 Devices 5.3. Intel FPGA I/O IP Cores for Intel® Arria® 10 Devices 5.4. I/O Resources in Intel® Arria® 10 Devices 5.5. Architecture and General Features of I/Os in Intel® Arria® 10 Devices 5.6. High Speed Source-Synchronous SERDES and DPA in Intel® Arria® 10 Devices 5.7. Using the I/Os and High Speed I/Os in Intel® Arria® 10 Devices 5.8. I/O and High Speed I/O in Intel® Arria® 10 Devices Revision History
5.2. I/O Standards and Voltage Levels in Intel® Arria® 10 Devices x
5.2.1. I/O Standards Support for FPGA I/O in Intel® Arria® 10 Devices 5.2.2. I/O Standards Support for HPS I/O in Intel® Arria® 10 Devices 5.2.3. I/O Standards Voltage Levels in Intel® Arria® 10 Devices
5.4. I/O Resources in Intel® Arria® 10 Devices x
5.4.1. GPIO Banks, SERDES, and DPA Locations in Intel® Arria® 10 Devices 5.4.2. GPIO Buffers and LVDS Channels in Intel® Arria® 10 Devices 5.4.3. I/O Banks Groups in Intel® Arria® 10 Devices 5.4.4. I/O Vertical Migration for Intel® Arria® 10 Devices
5.4.2. GPIO Buffers and LVDS Channels in Intel® Arria® 10 Devices x
5.4.2.1. FPGA I/O Resources in Intel® Arria® 10 GX Packages 5.4.2.2. FPGA I/O Resources in Intel® Arria® 10 GT Packages 5.4.2.3. FPGA I/O Resources in Intel® Arria® 10 SX Packages
5.4.3. I/O Banks Groups in Intel® Arria® 10 Devices x
5.4.3.1. I/O Banks for Intel® Arria® 10  GX Devices 5.4.3.2. I/O Banks for Intel® Arria® 10  GT Devices 5.4.3.3. I/O Banks for Intel® Arria® 10  SX Devices
5.4.4. I/O Vertical Migration for Intel® Arria® 10 Devices x
5.4.4.1. Verifying Pin Migration Compatibility
5.5. Architecture and General Features of I/Os in Intel® Arria® 10 Devices x
5.5.1. I/O Element Structure in Intel® Arria® 10 Devices 5.5.2. Features of I/O Pins in Intel® Arria® 10 Devices 5.5.3. Programmable IOE Features in Intel® Arria® 10 Devices 5.5.4. On-Chip I/O Termination in Intel® Arria® 10 Devices 5.5.5. External I/O Termination for Intel® Arria® 10 Devices
5.5.1. I/O Element Structure in Intel® Arria® 10 Devices x
5.5.1.1. I/O Bank Architecture in Intel® Arria® 10 Devices 5.5.1.2. I/O Buffer and Registers in Intel® Arria® 10 Devices
5.5.2. Features of I/O Pins in Intel® Arria® 10 Devices x
5.5.2.1. Open-Drain Output 5.5.2.2. Bus-Hold Circuitry 5.5.2.3. Weak Pull-up Resistor
5.5.3. Programmable IOE Features in Intel® Arria® 10 Devices x
5.5.3.1. Programmable Current Strength 5.5.3.2. Programmable Output Slew Rate Control 5.5.3.3. Programmable IOE Delay 5.5.3.4. Programmable Open-Drain Output 5.5.3.5. Programmable Pre-Emphasis 5.5.3.6. Programmable Differential Output Voltage
5.5.4. On-Chip I/O Termination in Intel® Arria® 10 Devices x
5.5.4.1. RS OCT without Calibration in Intel® Arria® 10 Devices 5.5.4.2. RS OCT with Calibration in Intel® Arria® 10 Devices 5.5.4.3. RT OCT with Calibration in Intel® Arria® 10 Devices 5.5.4.4. Dynamic OCT 5.5.4.5. Differential Input RD OCT 5.5.4.6. OCT Calibration Block in Intel® Arria® 10 Devices
5.5.5. External I/O Termination for Intel® Arria® 10 Devices x
5.5.5.1. Single-Ended I/O Termination 5.5.5.2. Differential I/O Termination for Intel® Arria® 10 Devices
5.5.5.2. Differential I/O Termination for Intel® Arria® 10 Devices x
5.5.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination 5.5.5.2.2. LVDS, RSDS, and Mini-LVDS Termination 5.5.5.2.3. LVPECL Termination
5.6. High Speed Source-Synchronous SERDES and DPA in Intel® Arria® 10 Devices x
5.6.1. Intel® Arria® 10 LVDS SERDES Usage Modes 5.6.2. SERDES Circuitry 5.6.3. SERDES I/O Standards Support in Intel® Arria® 10 Devices 5.6.4. Differential Transmitter in Intel® Arria® 10 Devices 5.6.5. Differential Receiver in Intel® Arria® 10 Devices 5.6.6. PLLs and Clocking for Intel® Arria® 10 Devices 5.6.7. Timing and Optimization for Intel® Arria® 10 Devices
5.6.4. Differential Transmitter in Intel® Arria® 10 Devices x
5.6.4.1. Transmitter Blocks in Intel® Arria® 10 Devices 5.6.4.2. Serializer Bypass for DDR and SDR Operations
5.6.5. Differential Receiver in Intel® Arria® 10 Devices x
5.6.5.1. Receiver Blocks in Intel® Arria® 10 Devices 5.6.5.2. Receiver Modes in Intel® Arria® 10 Devices
5.6.5.1. Receiver Blocks in Intel® Arria® 10 Devices x
5.6.5.1.1. DPA Block 5.6.5.1.2. Synchronizer 5.6.5.1.3. Data Realignment Block (Bit Slip) 5.6.5.1.4. Deserializer
5.6.5.2. Receiver Modes in Intel® Arria® 10 Devices x
5.6.5.2.1. Non-DPA Mode 5.6.5.2.2. DPA Mode 5.6.5.2.3. Soft-CDR Mode
5.6.6. PLLs and Clocking for Intel® Arria® 10 Devices x
5.6.6.1. Clocking Differential Transmitters 5.6.6.2. Clocking Differential Receivers 5.6.6.3. Guideline: LVDS Reference Clock Source 5.6.6.4. Guideline: Use PLLs in Integer PLL Mode for LVDS 5.6.6.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only 5.6.6.6. Guideline: Pin Placement for Differential Channels 5.6.6.7. LVDS Interface with External PLL Mode
5.6.6.2. Clocking Differential Receivers x
5.6.6.2.1. Guideline: Clocking DPA Interfaces Spanning Multiple I/O Banks 5.6.6.2.2. Guideline: I/O PLL Reference Clock Source for DPA or Non-DPA Receiver
5.6.6.7. LVDS Interface with External PLL Mode x
5.6.6.7.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.6.6.7.2. IOPLL Parameter Values for External PLL Mode 5.6.6.7.3. Connection between IOPLL and LVDS SERDES in External PLL Mode
5.6.7. Timing and Optimization for Intel® Arria® 10 Devices x
5.6.7.1. Source-Synchronous Timing Budget
5.6.7.1. Source-Synchronous Timing Budget x
5.6.7.1.1. Differential Data Orientation 5.6.7.1.2. Differential I/O Bit Position 5.6.7.1.3. Transmitter Channel-to-Channel Skew 5.6.7.1.4. Receiver Skew Margin for Non-DPA Mode
5.7. Using the I/Os and High Speed I/Os in Intel® Arria® 10 Devices x
5.7.1. I/O and High-Speed I/O General Guidelines for Intel® Arria® 10 Devices 5.7.2. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards 5.7.3. Guideline: Maximum Current Driving I/O Pins While Turned Off and During Power Sequencing 5.7.4. Guideline: Using the I/O Pins in HPS Shared I/O Banks 5.7.5. Guideline: Maximum DC Current Restrictions 5.7.6. Guideline: LVDS SERDES IP Core Instantiation 5.7.7. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode 5.7.8. Guideline: Minimizing High Jitter Impact on Intel® Arria® 10 GPIO Performance 5.7.9. Guideline: Usage of I/O Bank 2A for External Memory Interfaces
5.7.1. I/O and High-Speed I/O General Guidelines for Intel® Arria® 10 Devices x
5.7.1.1. Guideline: VREF Sources and VREF Pins 5.7.1.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing 5.7.1.3. Guideline: I/O Standards Supported for I/O PLL Reference Clock Input Pin
5.7.2. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards x
5.7.2.1. Non-Voltage-Referenced I/O Standards 5.7.2.2. Voltage-Referenced I/O Standards 5.7.2.3. Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards
6. External Memory Interfaces in Intel® Arria® 10 Devices x
6.1. Key Features of the Intel® Arria® 10 External Memory Interface Solution 6.2. Memory Standards Supported by Intel® Arria® 10 Devices 6.3. External Memory Interface Widths in Intel® Arria® 10 Devices 6.4. External Memory Interface I/O Pins in Intel® Arria® 10 Devices 6.5. Memory Interfaces Support in Intel® Arria® 10 Device Packages 6.6. External Memory Interface IP Support in Intel® Arria® 10 Devices 6.7. External Memory Interface Architecture of Intel® Arria® 10 Devices 6.8. External Memory Interface in Intel® Arria® 10 Devices Revision History
6.4. External Memory Interface I/O Pins in Intel® Arria® 10 Devices x
6.4.1. Guideline: Usage of I/O Bank 2A for External Memory Interfaces
6.5. Memory Interfaces Support in Intel® Arria® 10 Device Packages x
6.5.1. Intel® Arria® 10 Package Support for DDR3 x40 with ECC 6.5.2. Intel® Arria® 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank 6.5.3. Intel® Arria® 10 Package Support for DDR4 x40 with ECC 6.5.4. Intel® Arria® 10 Package Support for DDR4 x72 with ECC Single-Rank 6.5.5. Intel® Arria® 10 Package Support for DDR4 x72 with ECC Dual-Rank 6.5.6. HPS External Memory Interface Connections in Intel® Arria® 10
6.5.6. HPS External Memory Interface Connections in Intel® Arria® 10 x
6.5.6.1. Intel® Arria® 10 Package Support for DDR3 x40 with ECC for HPS 6.5.6.2. Intel® Arria® 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank for HPS 6.5.6.3. Intel® Arria® 10 Package Support for DDR4 x40 with ECC for HPS 6.5.6.4. Intel® Arria® 10 Package Support for DDR4 x72 with ECC Single-Rank for HPS
6.6. External Memory Interface IP Support in Intel® Arria® 10 Devices x
6.6.1. Ping Pong PHY IP
6.7. External Memory Interface Architecture of Intel® Arria® 10 Devices x
6.7.1. I/O Bank 6.7.2. I/O AUX
6.7.1. I/O Bank x
6.7.1.1. Hard Memory Controller 6.7.1.2. Delay-Locked Loop 6.7.1.3. Sequencer 6.7.1.4. Clock Tree 6.7.1.5. I/O Lane
6.7.1.1. Hard Memory Controller x
6.7.1.1.1. Hard Memory Controller Features 6.7.1.1.2. Main Control Path 6.7.1.1.3. Data Buffer Controller
6.7.1.5. I/O Lane x
6.7.1.5.1. DQS Logic Block
7. Configuration, Design Security, and Remote System Upgrades in Intel® Arria® 10 Devices x
7.1. Enhanced Configuration and Configuration via Protocol 7.2. Configuration Schemes 7.3. Configuration Details 7.4. Remote System Upgrades Using Active Serial Scheme 7.5. Design Security 7.6. Configuration, Design Security, and Remote System Upgrades in Intel® Arria® 10 Devices Revision History
7.2. Configuration Schemes x
7.2.1. Active Serial Configuration 7.2.2. Passive Serial Configuration 7.2.3. Fast Passive Parallel Configuration 7.2.4. JTAG Configuration
7.2.1. Active Serial Configuration x
7.2.1.1. DATA Clock (DCLK) 7.2.1.2. Active Serial Single-Device Configuration 7.2.1.3. Active Serial Multi-Device Configuration 7.2.1.4. Active Serial Configuration with Multiple EPCQ-L Devices 7.2.1.5. Using EPCQ-L Devices
7.2.1.3. Active Serial Multi-Device Configuration x
7.2.1.3.1. Pin Connections and Guidelines 7.2.1.3.2. Using Multiple Configuration Data
7.2.1.5. Using EPCQ-L Devices x
7.2.1.5.1. Controlling EPCQ-L Devices 7.2.1.5.2. Trace Length Guideline 7.2.1.5.3. Programming EPCQ-L Devices
7.2.2. Passive Serial Configuration x
7.2.2.1. Passive Serial Single-Device Configuration Using an External Host 7.2.2.2. Passive Serial Single-Device Configuration Using an Intel FPGA Download Cable 7.2.2.3. Passive Serial Multi-Device Configuration
7.2.2.3. Passive Serial Multi-Device Configuration x
7.2.2.3.1. Pin Connections and Guidelines 7.2.2.3.2. Using Multiple Configuration Data 7.2.2.3.3. Using One Configuration Data 7.2.2.3.4. Using PC Host and Download Cable
7.2.3. Fast Passive Parallel Configuration x
7.2.3.1. Fast Passive Parallel Single-Device Configuration 7.2.3.2. Fast Passive Parallel Multi-Device Configuration
7.2.3.2. Fast Passive Parallel Multi-Device Configuration x
7.2.3.2.1. Pin Connections and Guidelines 7.2.3.2.2. Using Multiple Configuration Data 7.2.3.2.3. Using One Configuration Data
7.2.4. JTAG Configuration x
7.2.4.1. JTAG Single-Device Configuration 7.2.4.2. JTAG Multi-Device Configuration
7.2.4.2. JTAG Multi-Device Configuration x
7.2.4.2.1. Pin Connections and Guidelines 7.2.4.2.2. Using a Download Cable
7.3. Configuration Details x
7.3.1. MSEL Pin Settings 7.3.2. CLKUSR 7.3.3. Configuration Sequence 7.3.4. Configuration Timing Waveforms 7.3.5. Estimating Configuration Time 7.3.6. Device Configuration Pins 7.3.7. Configuration Data Compression
7.3.3. Configuration Sequence x
7.3.3.1. Power Up 7.3.3.2. Reset 7.3.3.3. Configuration 7.3.3.4. Configuration Error Handling 7.3.3.5. Initialization 7.3.3.6. User Mode
7.3.3.3. Configuration x
7.3.3.3.1. Configuration Error Detection
7.3.4. Configuration Timing Waveforms x
7.3.4.1. FPP Configuration Timing 7.3.4.2. AS Configuration Timing 7.3.4.3. PS Configuration Timing
7.3.6. Device Configuration Pins x
7.3.6.1. I/O Standards and Drive Strength for Configuration Pins 7.3.6.2. Configuration Pin Options in the Intel® Quartus® Prime Software
7.3.7. Configuration Data Compression x
7.3.7.1. Enabling Compression Before Design Compilation 7.3.7.2. Enabling Compression After Design Compilation 7.3.7.3. Using Compression in Multi-Device Configuration
7.4. Remote System Upgrades Using Active Serial Scheme x
7.4.1. Configuration Images 7.4.2. Configuration Sequence in the Remote Update Mode 7.4.3. Remote System Upgrade Circuitry 7.4.4. Enabling Remote System Upgrade Circuitry 7.4.5. Remote System Upgrade Registers 7.4.6. Remote System Upgrade State Machine 7.4.7. User Watchdog Timer
7.4.5. Remote System Upgrade Registers x
7.4.5.1. Control Register 7.4.5.2. Status Register
7.5. Design Security x
7.5.1. Security Key Types 7.5.2. Security Modes 7.5.3. Intel® Arria® 10 Qcrypt Security Tool 7.5.4. Design Security Implementation Steps
7.5.2. Security Modes x
7.5.2.1. JTAG Secure Mode
8. SEU Mitigation for Intel® Arria® 10 Devices x
8.1. Intel® Arria® 10 SEU Mitigation Overview 8.2. Intel® Arria® 10 SEU Mitigation Techniques 8.3. CRAM Error Detection Settings Reference 8.4. Specifications 8.5. SEU Mitigation for Intel® Arria® 10 Devices Revision History
8.1. Intel® Arria® 10 SEU Mitigation Overview x
8.1.1. Mitigating Single Event Upset
8.1.1. Mitigating Single Event Upset x
8.1.1.1. Configuration RAM 8.1.1.2. Embedded Memory 8.1.1.3. Failure Rates
8.2. Intel® Arria® 10 SEU Mitigation Techniques x
8.2.1. Mitigating SEU Effects in Configuration RAM 8.2.2. Mitigating SEU Effects in Embedded User RAM 8.2.3. Triple-Module Redundancy 8.2.4. Intel® Quartus® Prime Software SEU FIT Reports
8.2.1. Mitigating SEU Effects in Configuration RAM x
8.2.1.1. Error Detection Cyclic Redundancy Check 8.2.1.2. SEU Sensitivity Processing 8.2.1.3. Hierarchy Tagging 8.2.1.4. Evaluating Your System’s Response to Functional Upsets 8.2.1.5. Recovering from CRC Errors
8.2.1.1. Error Detection Cyclic Redundancy Check x
8.2.1.1.1. Column-Based and Frame-Based Check-Bits 8.2.1.1.2. Error Message Register 8.2.1.1.3. CRC_ERROR Pin Behavior
8.2.1.5. Recovering from CRC Errors x
8.2.1.5.1. Enabling Error Correction (Internal Scrubbing)
8.2.2. Mitigating SEU Effects in Embedded User RAM x
8.2.2.1. Configuring RAM to Enable ECC
8.2.4. Intel® Quartus® Prime Software SEU FIT Reports x
8.2.4.1. SEU FIT Parameters Report 8.2.4.2. Projected SEU FIT by Component Usage Report 8.2.4.3. Enabling the Projected SEU FIT by Component Usage Report
8.2.4.2. Projected SEU FIT by Component Usage Report x
8.2.4.2.1. Component FIT Rates 8.2.4.2.2. Raw FIT 8.2.4.2.3. Utilized FIT 8.2.4.2.4. Mitigated FIT 8.2.4.2.5. Architectural Vulnerability Factor
8.4. Specifications x
8.4.1. Error Detection Frequency 8.4.2. Error Detection Time 8.4.3. EMR Update Interval 8.4.4. Error Correction Time
9. JTAG Boundary-Scan Testing in Intel® Arria® 10 Devices x
9.1. BST Operation Control 9.2. I/O Voltage for JTAG Operation 9.3. Performing BST 9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry 9.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing 9.6. IEEE Std. 1149.1 Boundary-Scan Register 9.7. JTAG Boundary-Scan Testing in Intel® Arria® 10 Devices Revision History
9.1. BST Operation Control x
9.1.1. IDCODE 9.1.2. Supported JTAG Instruction 9.1.3. JTAG Secure Mode 9.1.4. JTAG Private Instruction
9.6. IEEE Std. 1149.1 Boundary-Scan Register x
9.6.1. Boundary-Scan Cells of an Intel® Arria® 10 Device I/O Pin 9.6.2. IEEE Std. 1149.6 Boundary-Scan Register
10. Power Management in Intel® Arria® 10 Devices x
10.1. Power Consumption 10.2. Power Reduction Techniques 10.3. Power Sense Line 10.4. Voltage Sensor 10.5. Temperature Sensing Diode 10.6. Power-On Reset Circuitry 10.7. Power Sequencing Considerations for Intel® Arria® 10 Devices 10.8. Power Supply Design 10.9. Power Management in Intel® Arria® 10 Devices Revision History
10.1. Power Consumption x
10.1.1. Dynamic Power Equation
10.2. Power Reduction Techniques x
10.2.1. SmartVID 10.2.2. Programmable Power Technology 10.2.3. Low Static Power Device Grades 10.2.4. SmartVID Feature Implementation
10.4. Voltage Sensor x
10.4.1. Input Signal Range for External Analog Signal 10.4.2. Using Voltage Sensor in Intel® Arria® 10 Devices
10.4.1. Input Signal Range for External Analog Signal x
10.4.1.1. Unipolar Input Mode
10.4.2. Using Voltage Sensor in Intel® Arria® 10 Devices x
10.4.2.1. Accessing the Voltage Sensor Using FPGA Core Access 10.4.2.2. Voltage Sensor Transfer Function
10.4.2.1. Accessing the Voltage Sensor Using FPGA Core Access x
10.4.2.1.1. Configuration Registers for the Core Access Mode 10.4.2.1.2. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11 10.4.2.1.3. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11
10.5. Temperature Sensing Diode x
10.5.1. Internal Temperature Sensing Diode 10.5.2. External Temperature Sensing Diode 10.5.3. Design Consideration
10.5.1. Internal Temperature Sensing Diode x
10.5.1.1. Transfer Function for Internal TSD
10.5.3. Design Consideration x
10.5.3.1. Comparing Temperature Readouts of Intel® Arria® 10 External TSD and Intel® Arria® 10 Internal Temperature Sensor
10.6. Power-On Reset Circuitry x
10.6.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
10.7. Power Sequencing Considerations for Intel® Arria® 10 Devices x
10.7.1. Power-Up Sequence Requirements for Intel® Arria® 10 Devices 10.7.2. Power-Down Sequence Recommendations and Requirements for Intel® Arria® 10 Devices
1. Logic Array Blocks and Adaptive Logic Modules in Intel® Arria® 10 Devices
2. Embedded Memory Blocks in Intel® Arria® 10 Devices
3. Variable Precision DSP Blocks in Intel® Arria® 10 Devices
4. Clock Networks and PLLs in Intel® Arria® 10 Devices
5. I/O and High Speed I/O in Intel® Arria® 10 Devices
6. External Memory Interfaces in Intel® Arria® 10 Devices
7. Configuration, Design Security, and Remote System Upgrades in Intel® Arria® 10 Devices
8. SEU Mitigation for Intel® Arria® 10 Devices
9. JTAG Boundary-Scan Testing in Intel® Arria® 10 Devices
10. Power Management in Intel® Arria® 10 Devices

5.8. I/O and High Speed I/O in Intel® Arria® 10 Devices Revision History

Document Version Changes
2023.10.25
  • Clarified in the Supported I/O Standards in FPGA I/O for Intel® Arria® 10 Devices that SSTL- 12, SSTL -12 Class I and Class II are supportable for 3V I/O buffer type.
  • Updated the Guideline: Pin Placement for Differential Channels chapter for better clarity.
  • Added the Guideline: LVDS Reference Clock Source topic.
  • Removed the RSKM Report for LVDS Receiver topic.
2023.01.18 Added LVDS, RSDS, mini-LVDS, Differential POD12, and LVPECL to the list of I/O standards that support programmable I/O delay.
2022.09.29
  • Updated the outclk2 and outclk4 phase shift values in the topic listing the IOPLL parameter values for external PLL mode.
  • Added .qsf assignment information for on-chip differential I/O termination.
  • In the guideline for VREF sources and VREF pins, clarified that the internal VREF is supported only for external memory interfaces.
2021.08.13 Updated the table that lists the SERDES transmitter I/O standards support to remove all previously listed I/O standards except True LVDS, mini-LVDS, and RSDS.
2020.11.05 Updated the pin placement guidelines for differential channels to clarify that the I/O bank PLL can drive transmitter channels in an adjacent I/O bank only in a wide transmitter interface that spans multiple I/O banks.
2020.06.30 Added a footnote to table Intel Arria 10 I/O Standards Voltage Levels in section I/O Standards Voltage Levels in Intel® Arria® 10 Devices.
2019.12.30 Updated the programmable pre-emphasis diagram to remove the word "peak-peak".
2019.05.06 Added a topic that provides a usage modes summary of the Intel® Arria® 10 LVDS SERDES.
2019.01.11
  • Removed statement that says that the programmable VOD value of "0" is not available for the LVDS I/O standard.
  • Removed ext_loaden signal in figures showing the LVDS receiver in soft-CDR mode.
  • Specified that connecting the IOPLL loaden signal to the LVDS receiver ext_loaden signal is not required for LVDS receivers in soft-CDR mode.
  • Updated the VREF sources and pins guideline to specify that the internal VREF is supported only for the POD12 I/O standard.
2018.08.28
  • Removed the MultiVolt I/O Interface in Intel® Arria® 10 Devices topic.
  • Updated the I/O Standards Voltage Levels in Intel® Arria® 10 Devices topic to add information about interfacing with systems of different voltages.
2018.04.17 Updated the table listing the OCT schemes supported in Intel® Arria® 10 devices to specify that 3 V I/O and HPS I/O do not support bidirectional OCT.
2018.03.09
  • Changed "logic-to-pin" to "logic to the output buffer" in the topic about programmable open-drain output.
  • In the guideline topic about pin placement for differential channels, clarified that in an I/O bank where a DPA channel is enabled, you can assign unused pins an I/O standard that has the same VCCIO as the I/O bank.
  • Added link to the Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide for more information about using internal VREF for the POD 12 I/O standards.
  • Removed the guideline topic about not driving I/O pins during power sequencing.
  • Added guideline topic about maximum currents driving through I/O pins on LVDS I/O banks while turned off and during power sequencing.
  • Changed the term "modular I/O bank" to "I/O bank". In Intel® Arria® 10 devices, all I/O banks are modular.
Date Version Changes
December 2017 2017.12.15
  • Added SSTL-12, SSTL-125, SSTL135, Differential SSTL-12, Differential SSTL-125, and Differential SSTL-135 I/O standards into Supported I/O Standards in FPGA I/O for Intel® Arria® 10 Devices and Intel® Arria® 10 I/O Standards Voltage Levels tables.
  • Removed DDR3 OCT Setting from Programmable Current Strength Settings for Intel® Arria® 10 Devices table and added a note to refer to On-Chip I/O Termination in Intel® Cyclone® 10 GX Devices section for I/O standards with DDR3 OCT Setting.
  • Added a note to the topic about the open-drain output to specify that you must not pull the output voltage higher than the Vi (DC) level.
  • Updated the table listing the programmable current strength to update the 3.0 V LVTTL current strength settings—added 24 mA and 20 mA, and specified 16 mA as the default setting.
  • Updated the note about driving LVDS channels with the PLL in integer PLL mode to clarify that you do not need a PLL if you bypass the SERDES.
  • Updated the topic about the serializer bypass for DDR and SDR operation to add more information about clocks to the IOE.
  • Updated the topic about the deserializer to add more information about bypassing the deserializer.
  • Removed the statement about SDR and DDR data width from the figures that show the receiver datapath in non-DPA, DPA, and soft-CDR modes.
  • Corrected typographical error in the example showing the parameter values to generate output clock in external PLL mode by updating "c0" to "outclk0".
  • Updated the figure titles in the topic about LVPECL termination to clarify that the figures refer to external termination. There is no OCT support for LVPECL I/O standard.
  • Updated the RSKM calculation example.
  • Updated several links and link titles.
  • Clarified that I/O banks used for differential receiver, the PLL can drive only the channels within the same I/O bank in Guideline: Pin Placement for Differential Channels.
  • Added Intel FPGA PHYLite for Parallel Interfaces IP core description in FPGA I/O IP Cores for Intel® Arria® 10 Devices.
  • Clarified that to utilize the I/O registers when implementing DDR circuitry, use the Intel FPGA GPIO IP core in I/O Buffer and Registers in Intel® Arria® 10 Devices.
  • Clarified that 3 V I/O bank supports single-ended and differential SSTL, HSTL, and HSUL I/O standards.
  • Clarified that all singled-ended I/O configured to 3 V I/O bank supports all programmable I/O elements except programmable pre-emphasis, RD on-chip termination (OCT), calibrated RS and RT OCT, and internal VREF generation.
  • Updated I/O and Differential I/O Buffers in Intel® Arria® 10 Devices topic that differential reference clock is supported for the I/O PLL that drives the SERDES.
  • Specified that VREF pins are dedicated for voltage-reference signal-ended I/O standards in Guideline: VREF Sources and VREF Pins.
  • Clarified the type of I/O buffers available in Intel® Arria® 10 FPGA devices and Intel® Arria® 10 SoC devices in I/O Standards and Voltage Levels in Intel® Arria® 10 Devices.
May 2017 2017.05.08
  • Updated the vertical migration table to remove vertical migration between Intel® Arria® 10 GX and Intel® Arria® 10 SX device variants.
  • Updated the topic about the LVDS interface with external PLL mode to clarify that the Clock Resource Summary tab in the LVDS SERDES IP core parameter editor provides the details for the signals required from the GPIO IP core.
  • Updated the table that lists the programmable IOE features supported by the I/O buffer types and I/O standards.
  • Removed all "Preliminary" marks.
March 2017 2017.03.15 Rebranded as Intel.
October 2016 2016.10.31
  • Added information about the default predefined current strength if you do not specifically assign a current strength in the Intel® Quartus® Prime software.
  • Updated the topic about OCT calibration block to verify that you can calibrate the OCT using OCT calibration block in any I/O bank of the same I/O column.
  • Removed the F36 package from the Intel® Arria® 10 GX device family variant.
  • Updated the topic about receiver skew margin for non-DPA mode to clarify TCCS and RCCS usage in calculating the RSKM value.
  • Updated the guideline about not driving the I/O pins during power sequencing to stress that excess I/O pin current can affect device reliability and damage the device.
June 13 2016.06.13
  • Updated the I/O vertical migration figure to add the KF40 package for the SX 570 and SX 660 devices.
  • Updated the table listing the I/O standards voltage levels to add 2.5 V input to 3.0 V LVTTL/3.0 V LVCMOS, and 3.0 V input to 2.5 V LVCMOS.
May 2016 2016.05.02
  • Removed the NF40 and UF45 packages from the Intel® Arria® 10 GT device family variant.
  • Corrected the modular I/O banks information for the Intel® Arria® 10 GT 1150 device by updating the package from NF45 to SF45.
  • Updated the tables listing the I/O standards to clarify Class I and Class II support for SSTL-12, SSTL-125, SSTL-135, Differential SSTL-12, Differential SSTL-125, and Differential SSTL-135 I/O standards.
  • Corrected the table listing programmable IOE features to remove differential output voltage support for 3 V I/O banks.
  • Updated the list of programmable current strengths to add support for SSTL-135, SSTL-125, SSTL-12, POD-12, Differential SSTL-135, Differential SSTL-125, Differential SSTL-12, and Differential POD12 I/O standards.
  • Added 120 Ω OCT option for SSTL-12 and Differential SSTL-12 I/O standards.
  • Added guideline about clocking DPA interfaces that use more than 24 channels.
  • Added guideline about the I/O PLL reference clock source.
  • Added guideline about the I/O standards supported for the I/O PLL reference clock input pin.
  • Added guideline about using I/O pins in the HPS shared I/O banks.
  • Updated the maximum DC current restrictions guideline topic to specify that there are no restrictions for any number of consecutive I/O pins.
  • Updated the topics about using the LVDS interface with external PLL mode. The update adds examples and connection diagrams for using transmitter channels that span multiple banks and shared with receiver channels in DPA and soft-CDR modes.
  • Removed the restriction of using I/O bank 2A for external memory interfaces and added guidelines for using I/O bank 2A for external memory interfaces.
December 2015 2015.12.14
  • Updated the table listing the I/O standards voltage support to remove 3.0 V VCCIO input from the 2.5 V I/O standard.
  • Updated the topic about MultiVolt I/O interface to update VCCP to VCC.
  • Corrected the I/O standards supported for the open-drain output, bus-hold, and weak pull-up resistor features in the table summarizing the programmable IOE features.
  • Updated the topic about the data realignment block (bit slip) to specify that valid data is available four parallel clock cycles after the rising edge of rx_bitslip_ctrl. Previously, valid data is available after two parallel clock cycles.
  • Updated the topic about external I/O termination for devices to add footnotes about using OCT for SSTL-12 and Differential SSTL-12 I/O standards, and note about recommendation to perform IBIS or SPICE simulations.
  • Updated the topic about uncalibrated RS OCT:
    • Updated the RS values of SSTL-15 to remove 25 Ω and 50 Ω.
    • Added the Differential SSTL-15, Differential SSTL-135, Differential SSTL-125, Differential SSTL-12, Differential POD12, and Differential HSUL-12 I/O standards.
  • Updated the topic about calibrated RS OCT to add the Differential POD12 I/O standard.
  • Updated the topic about calibrated RT OCT to remove 20 Ω RT OCT support and to add the Differential POD12 I/O standard.
  • Removed the Differential SSTL-2 Class I and Class II I/O standards from the tables listing the SERDES receiver and transmitter I/O standards support.
  • Updated the topic about the voltage-referenced I/O standard under the guideline for mixing voltage-referenced and non-voltage-referenced I/O standards.
  • Added design guideline for minimizing high jitter impact on the GPIO performance.
  • Updated the following signal names:
    • dpa_diffioclk to dpa_fast_clock
    • dpa_load_en to dpa_load_enable
November 2015 2015.11.02
  • Updated the topic about serializer bypass for SDR and DDR operations to specify that the serializer bypass is supported through the GPIO IP core.
  • Added a footnote with the definition of unit interval (UI) in the topic about the DPA block.
  • Updated the topic about the data realignment block (bit slip). The bit slip rollover value is now automatically set to the deserialization factor.
  • Updated the topic about the deserializer to specify that the deserializer bypass is supported through the GPIO IP core.
  • Updated the topic about PLLs and clocking to correct the parallel clock names from rx_outclock and tx_outclock to rx_coreclock and tx_coreclock.
  • Updated the topic about using the PLLs in integer mode for LVDS to clarify that the I/O PLLs operate in integer mode only.
  • Updated the following port/signal names:
    • rx_dpll_hold to rx_dpa_hold
    • rx_reset to rx_dpa_reset
    • rx_channel_data_align to rx_bitslip_ctrl
    • rx_cda_max to rx_bitslip_max
    • rx_outclock to rx_coreclock
    • lvds_diffioclk and diffioclk to fast_clock
    • lvds_load_en and load_en to load_enable
  • Updated the topic about pin placement for differential channels:
    • Improved clarity about PLLs driving interleaved differential transmitter and DPA-enabled receiver channels
    • Removed the note about bank placement DDIO and SDR I/Os
  • Updated the topic about the signal interface between IOPLL and the LVDS SERDES IP core in external PLL mode.
  • Updated the topic about IOPLL IP core parameter values for external PLL mode:
    • Phase shift of outclk0 from -180° to 180°
    • Phase shift of outclk2 from -180/serialization factor to 180/serialization factor (-18° to 18°)
  • Updated the definition of RSKM for the RSKM equation in the topic about the receiver skew margin in non-DPA mode.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.15 Corrected label for Intel® Arria® 10 GT product lines in the vertical migration figure.
May 2015 2015.05.04
  • Updated the statements in the topic about the I/O and differential I/O buffers to improve clarity.
  • Updated the I/O resources information for the U19 package of the Intel® Arria® 10 GX 160, GX 220, SX 160, and SX 220 devices:
    • Updated LVDS I/O count from 144 to 148
    • Updated total GPIO from 192 to 196
    • Updated number of LVDS channels from 72 to 74
    • Added bank 3A and removed bank 3C in the figures and related modular I/O banks tables
  • Updated the figure showing the IOE structure to clarify that the delay chains are separate.
  • Updated the modular I/Os for banks 3A (from null to 48) and 3B (from 48 to null) for the F27 package of the Intel® Arria® 10 GX 270, GX 320, SX 270, and SX 320 devices.
January 2015 2014.01.23
  • Added topic about programmable open-drain output.
  • Restructured the topic about pin placement for differential channels to enhance clarity.
  • Corrected contents that specified DPA-enabled transmitter channels. There is no DPA for transmitter channels.
  • Added guideline about instantiating only one Altera LVDS SERDES IP core instance for each I/O bank.
  • Added guideline about using only specific LVDS pin pairs in soft-CDR mode.
  • Updated the section that describes usage of the LVDS interface with external PLL:
    • Updated information about the required signals in Altera IOPLL and Altera LVDS SERDES IP cores.
    • Updated the examples of parameter values to generate output clocks using Altera IOPLL IP core.
    • Updated the LVDS clock phase relationship diagram for external PLL interface signals.
    • Updated the diagrams that show the connections between Altera IOPLL and Altera LVDS SERDES IP cores.
  • Added footnote to clarify that you can use pre-emphasis for LVDS and POD12 I/O standards. The POD12 I/O standard supports DDR4.
August 2014 2014.08.18
  • Updated description of the 3 V I/O bank regarding support for programmable IOE features.
  • Added statement to clarify that apart from FPGA I/O buffers, the Intel® Arria® 10 SoC devices also contains HPS I/O buffers with different I/O standards support.
  • Separated I/O bank 2A in each I/O banks location figures to signify that it is not consecutive with other I/O banks.
  • Updated LVDS I/O and SERDES circuitry descriptions to clarify that each LVDS channel have built-in transmit SERDES and receive SERDES.
  • Removed reference to on-chip clamping diode. Arria 10 devices do not have on-chip clamping diode. Use an external clamping diode where applicable.
  • Added a related information link to the Arria 10 Transceiver PHY User Guide that describes the transceiver I/O banks locations.
  • Updated the I/O vertical migration figure to show vertical migration between Arria 10 GX and Arria 10 SX devices.
  • Updated all references to "megafunction" to "IP core".
  • Updated all references to "MegaWizard Plug-in Manager" to "parameter editor".
  • Updated all references to Altera PLL IP core to Altera IOPLL IP core.
  • Updated the signal names for using the LVDS interface with the External PLL mode:
    • tx_inclock and rx_inclock to ext_fclk
    • tx_enable rx_enable to ext_loaden
    • rx_dpaclock to ext_vcoph[7..0]
    • rx_synclock to ext_coreclock
December 2013 2013.12.02 Initial release.
Level Two Title