Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 5/27/2022
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3.5.1.5.3. 27-Bit Systolic FIR Mode

In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation, providing 10 bits of overhead when using a 27-bit data (54-bit products).

The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per DSP block.

Figure 40.  27-Bit Systolic FIR Mode for Intel® Arria® 10 Devices


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