Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
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7.2.4.2.1. Pin Connections and Guidelines

Observe the following pin connections and guidelines for this configuration setup:

  • Isolate the CONF_DONE and nSTATUS pins to allow each device to enter user mode independently.
  • One JTAG-compatible header is connected to several devices in a JTAG chain. The number of devices in the chain is limited only by the drive capability of the download cable.
  • If you have four or more devices in a JTAG chain, buffer the TCK, TDI, and TMS pins with an on-board buffer. You can also connect other Intel FPGAs with JTAG support to the chain.
  • JTAG-chain device programming is ideal when the system contains multiple devices or when testing your system using the JTAG boundary-scan testing (BST) circuitry.