1.2.1. Normal Mode
Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic.
The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs.
The Intel® Quartus® Prime Compiler automatically selects the inputs to the LUT. ALMs in normal mode support register packing.
For the packing of two five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab).
In the case of implementing two six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. In a sparsely used device, functions that could be placed in one ALM may be implemented in separate ALMs by the Intel® Quartus® Prime software to achieve the best possible performance. As a device begins to fill up, the Intel® Quartus® Prime software automatically uses the full potential of the Intel® Arria® 10 ALM. The Intel® Quartus® Prime Compiler automatically searches for functions using common inputs or completely independent functions to be placed in one ALM to make efficient use of device resources. In addition, you can manually control resource use by setting location assignments.
You can implement any six-input function using the following inputs:
- datae0 and dataf1, or datae1 and dataf0
If you use datae0 and dataf1 inputs, you can obtain the following outputs:
- Output driven to register0 or register0 is bypassed
- Output driven to register1 or register1 is bypassed
You can use the datae1 or dataf0 input, whichever is available, as the packed register input to register2 or register3.
If you use datae1 and dataf0 inputs, you can obtain the following outputs:
- Output driven to register2 or register2 is bypassed
- Output driven to register3 or register3 is bypassed
You can use the datae0 or dataf1 input, whichever is available, as the packed register input to register0 or register1.