3.4.8. Systolic Registers for Fixed-Point Arithmetic
There are two systolic registers per variable precision DSP block. If the variable precision DSP block is not configured in fixed-point arithmetic systolic FIR mode, both systolic registers are bypassed.
The first set of systolic registers consists of 18-bit and 19-bit registers that are used to register the 18-bit and 19-bit inputs of the upper multiplier, respectively.
The second set of systolic registers are used to delay the chainin input from the previous variable precision DSP block.
You must clock all the systolic registers with the same clock source as the output register. Output registers must be turned on.