Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

6.7.1.5.1. DQS Logic Block

The DQS logic block contains:

  • Post-amble register
  • DQS delay chain
  • FIFO control
  • Multi-rank switch control block

DQS Delay Chain

The DQS delay chain provides variable delay to the DQS signal, allowing you to adjust the DQS signal timing during calibration to maximize the tsetup and thold for DQ capture.

To keep the delay value constant, the DQS delay chain also contains:

  • Logic to track temperature and low frequency voltage variation
  • Shadow registers to hold calibrated delay settings for multi-rank interfaces, and switch the DQS delay chain setting to one of up to four different settings.

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