- Removed LOCK and UNLOCK instructions from Mandatory IEEE Standard 1149.1 BST JTAG Instructions.
- Updated Single Device FPP Configuration Using an External Host, Multiple Device FPP Configuration Using an External Host When Both Devices Receive a Different Set of Configuration Data, and Multiple Device FPP Configuration Using an External Host When Both Devices Receive the Same Data figures.
- Rebranded as Intel.
- Added note to nIO_PULLUP pin in Configuration Pin Summary for Intel® Arria® 10 Devices table.
- Added pull-up resistor between nCEO and nCE in Multiple Device FPP Configuration Using an External Host When Both Devices Receive a Different Set of Configuration Data figure.
- Added pull-up resistor between nCEO and nCE in Multiple Device AS Configuration When Both Devices in the Chain Receive Different Sets of Configuration Data figure.
- Added pull-up resistor between nCEO and nCE in Multiple Device PS Configuration when Both Devices Receive Different Sets of Configuration Data figure.
- Updated the drive strength for configuration pins:
- DCLK—from 1.8 V CMOS 12 mA to 1.8 V CMOS 24 mA.
- NCSO[2..0]—from 1.8 V CMOS 8 mA to 1.8 V CMOS 12 mA.
- AS_DATA0/ASD0, AS_DATA1, AS_DATA2, and AS_DATA3—from 1.8 V CMOS 8 mA to 1.8 V CMOS 24 mA.
- Updated design security features and approaches.
- Updated instances of EX_JTAG_SECURE to EXT_JTAG_SECURE
- Added list of mandatory and non-mandatory IEEE Standard 1149.1 JTAG BST instructions.
- Updated security modes available in Arria 10 devices and instructions to enable them.
- Added the Qrypt security tool information.
- Added FPP and PS configuration time estimation to Estimating Configuration Time and moved subsection under Configuration Details section.
- Added note on possible PCIe timing violation when using direct-to-application.
- Added note on recommending user to set a fixed configuration image start address.
- Added I/O Standards and Drive Strength for Configuration Pins section.
- Updated AS configuration timing waveform to include nCSO.
- Updated TSU and TDH in AS configuration timing waveform.
- Updated CLKUSR information.
- Moved CLKUSR subsection from Active Serial Configuration to Configuration Details.
- Updated the term configuration mode to configuration scheme for consistency.
- Added link at MSEL pin setting to Arria 10 Hard Processor System Technical Reference Manual.
- Combined PS and FPP row in MSEL pin settings table. Both schemes have the same MSEL pin setting.
- Added description to MSEL pin setting table for configuration via HPS to use PS or FPP MSEL pin setting.
- Updated configuration modes and features table to include Yes for partial reconfiguration in JTAG, AS and PS configuration mode together with a footnote mentioning only if partial reconfiguration is configured as internal host.
- Updated note about compression and encryption cannot be used a the same time for all configuration scheme.
- Updated timing waveforms FPP, AS and PS to include pre power-up state.
- Removed step to select Remote from the Configuration mode list in the Configuration page of the Device and Pin Options dialog box in the Quartus II software.
- Added note about setting the MSEL pin to active serial to prevent EPCQ-L ID read failure during SFL programming.
- Changed instances of Quartus II to Quartus Prime.
- Added Timing waveforms for FPP, AS and PS configuration.
- Updated 'Trace Length and Loading' to 'Trace Length Guideline' and remove loading contents.
- Added link to Arria 10 Device Datasheet for loading information.
- Update FPP to support 8 and 32 bits in 'Configuration Modes and Features of Arria 10 Devices'.
- Added note in 'Design Security' and 'Configuration Data Compression' about compression and encryption cannot be used a the same time.
- Updated CLKUSR pin usage during AS configuration at 100 MHz.
- Updated Max clock rate of PS, FPP x8, FPP x16 and Configuration via HPS from 125 MHz to 100 MHz.
- Updated Remote System Upgrade Circuitry diagram by replacing RU_SHIFTnLD and RU_CAPTnUPDT to RU_CTL[1:0].
- Updated ALTREMOTE_UPDATE megafunction to Altera remote Update IP Core.
- Updated user watchdog time-out value from 34..46 to 34..45.
- Updated nIO_PULLUP to be powered by VCC.
- Added note to Max Data Rate in Configuration Modes and Features of Intel® Arria® 10 Devices table.
- Added the Active Serial Configuration with Multiple EPCQ-L Devices section.
- Removed the Unique Chip ID section.
- Updated the JTAG Configuration section to include details on the USB-Blaster download cable support.
- Updated the Power Up section.
- Updated Configuration Images section to include start address.
- Updated the Configuration Sequence in the Remote Update Mode section.
- Updated the Remote System Upgrade State Machine section.
- Updated Figure 7-18: JTAG Configuration of a Single Device Using a Microprocessor to update the power reference of the JTAG pins.
- Updated Figure 7-20: Configuration Sequence for Arria 10 Devices.
- Updated Figure 7-22: Arria 10 Remote System Upgrade Block Diagram.
- Updated Table 7-1: Configuration Modes and Features of Arria 10 Devices to update the supported clock rate for Partial Reconfiguration.
- Updated Table 7-3: MSEL Pin Settings for Each Configuration Scheme of Arria 10 Devices to include the supported VCCPGM voltages for the FPP and PS configuration schemes.
- Updated Table 7-6: Remote System Upgrade Registers to update the description for the shift, control, update, and status registers.
- Updated Table 7-7: Control Register Bits.
- Removed the Unique Chip ID section.