The sequencer implements a calibration algorithm to determine the combination of delay and phase settings that are necessary to maintain center-alignment of data and clock signals, even in the presence of significant delay variations. Programmable delay chains in the FPGA I/Os then implement the calculated delays to ensure that data remains centered.
A sequencer is embedded in every I/O bank. The sequencer is comprised of the following components:
- A read-write manager.
- An address/command set or instruction ROM.
- Helper modules such as PHY manager, data manager, and tracking manager.
- Data pattern and data out buffers on a per-pin basis that are managed by the read-write manager.
All major components of the sequencer are connected on the Avalon bus, providing controllability, visibility, and flexibility to the Nios II subsystem.
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