Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

6.5.2. Intel® Arria® 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank

To support one DDR3 x72 interface with ECC (64 bits data + 8 bits ECC) single and dual-rank, you require three I/O banks.

Table 77.  Number of DDR3 x72 Interfaces (with ECC) Single and Dual-rank Supported Per Device Package (without HPS Instance)
Note: For some device packages, you can also use the 3 V I/O banks for external memory interfaces. However, the maximum memory interface clock frequency is capped at 533 MHz. To use higher memory clock frequencies, exclude the 3 V I/O bank from external memory interfaces.
Product Line Package
U19 F27 F29 F34 F35 NF40 KF40 RF40 NF45 SF45 UF45
GX 160 116 1 16 116
GX 220 116 116 116
GX 270 116 216 216 216
GX 320 116 216 216 216
GX 480 216 316 216
GX 570 316 216 316 3
GX 660 316 216 316 3
GX 900 3 3 0 4 3 2
GX 1150 3 3 0 4 3 2
GT 900 3
GT 1150 3
SX 160 116 17 116 17 116 17
SX 220 116 17 116 17 116 17
SX 270 116 17 216 17 216 17 216 17
SX 320 116 17 216 17 216 17 216 17
SX 480 216 17 316 17 216 17
SX 570 316 17 216 17 316 17 3 17
SX 660 316 17 216 17 316 17 3 17
Table 78.  Number of DDR3 x72 Interfaces (with ECC) Single and Dual-rank Supported Per Device Package (with HPS Instance)The number of supported interfaces shown in this table excludes the interface used to connect the HPS to external SDRAM. Masters in the FPGA core can access the HPS-connected external memory interface via FPGA-to-SDRAM bridge ports configurable in the HPS.
Note: For some device packages, you can also use the 3 V I/O banks for external memory interfaces. However, the maximum memory interface clock frequency is capped at 533 MHz. To use higher memory clock frequencies, exclude the 3 V I/O bank from external memory interfaces.
Product Line Package
U19 F27 F29 F34 F35 NF40 KF40 RF40 NF45 SF45 UF45
SX 160 0 0 0
SX 220 0 0 0
SX 270 0 1 18 118 118
SX 320 0 1 18 118 1 18
SX 480 1 18 2 18 1 18
SX 570 2 18 1 18 2 18 2
SX 660 2 18 1 18 2 18 2
16 This number includes using the 3 V I/O bank for external memory interfaces. Otherwise, the number of external memory interfaces possible is reduced by one.
17 This number includes HPS shared I/O banks to implement core EMIF configurations.
18 This number includes using the 3 V I/O bank for external memory interfaces. Otherwise, the number of external memory interfaces possible is reduced by one.

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