Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 5/27/2022
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2.9. Memory Blocks Address Clock Enable Support

The embedded memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signal is low (disabled).

Figure 19. Address Clock EnableThis figure shows an address clock enable block diagram. The address clock enable is referred to by the port name addressstall.


Figure 20. Address Clock Enable During Read Cycle WaveformThis figure shows the address clock enable waveform during the read cycle.


Figure 21. Address Clock Enable During the Write Cycle WaveformThis figure shows the address clock enable waveform during the write cycle.


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