Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Document Table of Contents

9.2. I/O Voltage for JTAG Operation

The Intel® Arria® 10 device operating in IEEE Std. 1149.1 and IEEE Std. 1149.6 mode uses four required JTAG pins—TDI, TDO, TMS, TCK, and one optional pin, TRST.

The TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and TRST pins have internal weak pull-up resistors. The 1.8-, 1.5-, or 1.2-V VCCPGM supply powers the TDI, TDO, TMS, TCK, and TRST pins. All user I/O pins are tri-stated during JTAG configuration.

The JTAG pins support 1.8 V, 1.5V, and 1.2V TTL/CMOS I/O standard. For any voltages higher than 1.8 V, you have to use level shifter. The output voltage of the level shifter for the JTAG pins must be the same as set for the VCCPGM supply.

Note: Do not drive a signal with a voltage higher than 1.8-, 1.5-, and 1.2-V VCCPGM supply for the TDI, TMS, TCK, and TRST pins. The voltage supplies for TDI, TMS, TCK, and TRST input pins must be the same as set for the VCCPGM supply.
Table 118.  TDO Output Buffer
TDO Output Buffer Voltage (V)
VCCPGM 1.8 1.5 1.2
VOH (MIN) 1.7 1.4 1.1

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