Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

5.5.1.2. I/O Buffer and Registers in Intel® Arria® 10 Devices

I/O registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output enable (OE) path for handling the OE signal to the output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchronization. Use the GPIO Intel® FPGA IP to utilize these registers to implement DDR circuitry.

The input and output paths contain the following blocks:

  • Input registers—support half or full rate data transfer from peripheral to core, and support double or single data rate data capture from I/O buffer.
  • Output registers—support half or full rate data transfer from core to peripheral, and support double or single data rate data transfer to I/O buffer.
  • OE registers—support half or full rate data transfer from core to peripheral, and support single data rate data transfer to I/O buffer.

The input and output paths also support the following features:

  • Clock enable.
  • Asynchronous or synchronous reset.
  • Bypass mode for input and output paths.
  • Delays chains on input and output paths.
Figure 81. IOE Structure for Intel® Arria® 10 DevicesThis figure shows the Intel® Arria® 10 FPGA IOE structure.


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