Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 5/27/2022
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Document Table of Contents

8.5. SEU Mitigation for Intel® Arria® 10 Devices Revision History

Document Version Changes
2019.09.06 Updated the topic about failure rates to correct the number of years of one billion hours.
2018.06.08 Added Failure Rates, Configurating RAM to Enable ECC, Triple Module Redundancy, Software SEU FIT Reports and sub-sections, and CRAM Error Detection Settings Reference sections.
2018.03.09 Added missing figure in SEU Sensitivity Processing.
Date Version Changes
March 2017 2017.03.15 Rebranded as Intel.
May 2016 2016.05.02
  • Edited Error Detection Cyclic Redundancy Check.
  • Updated CRC check bit instances to column-based check-bits and frame-based check-bits.
  • Updated Error Message Register Map figure.
  • Added Fast EDCRC Process Flow Chartfigure.
  • Added note stating that there is no significant power benefit from reducing error detection frequency.
December 2015 2015.12.14
  • Updated chapter structure.
  • Added Error Correction Time specification.
  • Added brief description and external related information link for Embedded Memory, Memory Blocks Error Correction Code Support, SEU Sensitivity, Hierarchy Tagging, and Evaluating your System Response to SEU.
  • Updated divisor value in Error Detection Frequency.
  • Updated Error Detection Frequency Range table showing fMAX and fMIN.
  • Updated Estimated EMR Update Interval and CRC Calculation Time table.
  • Added equation for EMR update interval and CRC calculation time.
November 2015 2015.11.02 Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.15 Updated links to Altera EMR Unloader IP Core User Guide, Altera Fault Injection IP Core User Guide and Altera Advance SEU Detection IP Core User Guide.
May 2015 2015.05.04
  • Added links to Altera EMR Unloader IP Core User Guide, Altera Fault Injection IP Core User Guide and Altera Advance SEU Detection IP Core User Guide.
  • Updated CRC_ERROR pin behavior to included column-based and frame-based CRC error detection and frame-based only CRC error detection.
  • Updated column-based type in 'Error Type in EMR' at Bit 0.
  • Editorial changes.
  • Updated the divisor value and range for error detection frequency.
  • Updated CRC calculation time by including speed grade and rearranged accordingly.
  • Updated EMR update interval.
  • Updated Error Message Register Map and registers in Error Detection in User Mode block diagram.
January 2015 2015.01.23
  • Added EMR timing interval.
  • Added CRC calculation time.
  • Added timing diagram
August 2014 2014.08.18
  • Updated the Error Detection Features section.
  • Updated the Configuration Error Detection section to revise the CRC value.
  • Updated the User Mode Error Detection section to add in the check bits calculation for error detection CRC.
  • Updated the CRC_ERROR Pin Behavior section.
  • Updated the Retrieving Error Information section.
  • Updated the CRC_ERROR Pin section to update the pin description.
  • Updated Table 8-4 to updated the description of the frame-based syndrome register, user update register, and user shift register.
  • Updated Table 8-5 to update the error types naming to frame-based and column-based types.
December 2013 2013.12.02 Initial release.

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