Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

4.1.1. Clock Resources in Intel® Arria® 10 Devices

Table 27.  Clock Resources in Intel® Arria® 10 Devices
Clock Input Pins
Device Number of Resources Available Source of Clock Resource
  • 10AS016
  • 10AS022
  • 10AX016
  • 10AX022
  • HSSI: 4 differential
  • I/O: 32 single-ended or 16 differential
For high-speed serial interface (HSSI): REFCLK_GXB[L,R][1:4][C,D,E,F,G,H,I,J]_CH[B,T][p,n] pins

For I/O: CLK_[2,3][A..L]_[0,1][p,n] pins

  • 10AS027
  • 10AS032
  • 10AX027
  • 10AX032
  • HSSI: 8 differential
  • I/O: 32 single-ended or 16 differential
  • 10AS048
  • 10AX048
  • HSSI: 12 differential
  • I/O: 48 single-ended or 24 differential
  • 10AS057
  • 10AS066
  • 10AX057
  • 10AX066
  • HSSI: 16 differential
  • I/O: 64 single-ended or 32 differential
  • 10AT090
  • 10AT115
  • 10AX090
  • 10AX115
  • HSSI: 32 differential
  • I/O: 64 single-ended or 32 differential
GCLK Networks
Device Number of Resources Available Source of Clock Resource
All 32
  • Physical medium attachment (PMA) and physical coding sublayer (PCS) TX and RX clocks per channel
  • PMA and PCS TX and RX divide clocks per channel
  • Hard IP core clock output signals
  • DLL clock outputs
  • Fractional PLL (fPLL) and I/O PLL C counter outputs
  • I/O PLL M counter outputs for feedback
  • REFCLK and clock input pins
  • Core signals
  • Phase aligner counter outputs
RCLK Networks
Device Number of Resources Available Source of Clock Resource
  • 10AS016
  • 10AS022
  • 10AS027
  • 10AS032
  • 10AX016
  • 10AX022
  • 10AX027
  • 10AX032
8
  • Physical medium attachment (PMA) and physical coding sublayer (PCS) TX and RX clocks per channel
  • PMA and PCS TX and RX divide clocks per channel
  • Hard IP core clock output signals
  • DLL clock outputs
  • fPLL and I/O PLL C counter outputs
  • I/O PLL M counter outputs for feedback
  • REFCLK and clock input pins
  • Core signals
  • Phase aligner counter outputs
  • 10AS048
  • 10AX048
12
  • 10AS057
  • 10AS066
  • 10AX057
  • 10AX066
  • 10AT090
  • 10AT115
  • 10AX090
  • 10AX115
16
SPCLK Networks
Device Number of Resources Available Source of Clock Resource
  • 10AS016
  • 10AS022
  • 10AX016
  • 10AX022
  • 10AS027
  • 10AS032
  • 10AX027
  • 10AX032
144 For HSSI:
  • Physical medium attachment (PMA) and physical coding sublayer (PCS) TX and RX clocks per channel
  • PMA and PCS TX and RX divide clocks per channel
  • Hard IP core clock output signals
  • DLL clock outputs
  • fPLL C counter outputs
  • REFCLK and clock input pins
  • Core signals

For I/O:

  • DPA outputs (LVDS I/O only)
  • I/O PLL C and M counter outputs
  • Clock input pins
  • Core signals
  • Phase aligner counter outputs
  • 10AS048
  • 10AX048
216
  • 10AS057
  • 10AS066
  • 10AX057
  • 10AX066
288
  • 10AT090
  • 10AT115
  • 10AX090
  • 10AX115
384
LPCLK Networks
Device Number of Resources Available Source of Clock Resource
  • 10AS016
  • 10AS022
  • 10AX016
  • 10AX022
  • 10AS027
  • 10AS032
  • 10AX027
  • 10AX032
24 For HSSI:
  • Physical medium attachment (PMA) and physical coding sublayer (PCS) TX and RX clocks per channel
  • PMA and PCS TX and RX divide clocks per channel
  • Hard IP core clock output signals
  • DLL clock outputs
  • fPLL C and M counter outputs
  • REFCLK and clock input pins
  • Core signals

For I/O:

  • DPA outputs (LVDS I/O only)
  • I/O PLL C and M counter outputs
  • Clock input pins
  • Core signals
  • Phase aligner counter outputs
  • 10AS048
  • 10AX048
36
  • 10AS057
  • 10AS066
  • 10AX057
  • 10AX066
48
  • 10AT090
  • 10AT115
  • 10AX090
  • 10AX115
64

For more information about the clock input pins connections, refer to the pin connection guidelines.

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