8.2. Intel® Arria® 10 SEU Mitigation Techniques
Intel® Arria® 10 devices feature various single-event upset (SEU) mitigation approaches for different application areas.
|Area||SEU Mitigation Approach|
|Silicon design: CRAM/SRAMs/flip flops||Intel uses various design techniques to reduce upsets or limit to correctable double-bit errors.|
|Error Detection Cyclic redundancy check (EDCRC) / Scrubbing||You can enable the EDCRC feature for detecting CRAM SEU events and automatic correction of CRAM contents.|
|M20K SRAM block||Intel FPGA implements interleaving, special layout techniques, and Error Correction Code (ECC) to reduce SEU FIT rate to almost zero.|
|Sensitivity processing||You can use sensitivity processing to identify if the SEU in CRAM bit is a used or unused bit.|
|Fault injection||You can use fault injection feature to validate the system response to the SEU event by changing the CRAM state to trigger an error.|
|Hierarchical tagging||A complementary capability to sensitivity processing and fault injection for reporting SEU and constraining injection to specific portions of design logic.|
|Triple Modular Redundancy (TMR)||You can implement TMR technique on critical logic such as state machines.|
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