4.2.8. PLL Cascading
Intel® Arria® 10 devices support PLL-to-PLL cascading. You can only cascade a maximum of two PLLs. The cascaded PLLs must be adjacent PLLs. PLL cascading synthesizes more output clock frequencies than a single PLL.
If you cascade PLLs in your design, the source (upstream) PLL must have a low-bandwidth setting and the destination (downstream) PLL must have a high-bandwidth setting. During cascading, the output of the source PLL serves as the reference clock (input) of the destination PLL. The bandwidth settings of cascaded PLLs must be different. If the bandwidth settings of the cascaded PLLs are the same, the cascaded PLLs may amplify phase noise at certain frequencies.
Intel® Arria® 10 devices only support I/O-PLL-to-I/O-PLL cascading via dedicated cascade path for core applications. In this mode, upstream I/O PLL and downstream I/O PLL must be located within the same I/O column.
Intel® Arria® 10 fPLL does not support PLL cascading mode for core applications.