Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

7.2.1.3.1. Pin Connections and Guidelines

Observe the following pin connections and guidelines for this configuration setup:

  • Hardwire the MSEL pins of the first device in the chain to select the AS configuration scheme. For subsequent devices in the chain, hardwire their MSEL pins to select the PS configuration scheme. Any other Intel FPGAs that support the PS configuration can also be part of the chain as a configuration slave.
  • Tie the following pins of all devices in the chain together:
    • nCONFIG
    • nSTATUS
    • DCLK
    • DATA[]
    • CONF_DONE
    By tying the CONF_DONE , nSTATUS, and nCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.
  • Ensure that DCLK and DATA[] are buffered every fourth device to prevent signal integrity and clock skew problems.

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