Intel® Arria® 10 Device Datasheet

ID 683771
Date 2/14/2022
Public
Document Table of Contents

Programmable IOE Delay

Table 89.  IOE Programmable Delay for Intel® Arria® 10 Devices

For the exact values for each setting, use the latest version of the Intel® Quartus® Prime software. The values in the table show the delay of programmable IOE delay chain with maximum offset settings after excluding the intrinsic delay (delay at minimum offset settings).

Programmable IOE delay settings are only applicable for I/O buffers and do not apply for any other delay elements in the PHYLite for Parallel Interfaces Intel® Arria® 10 FPGA IP core.

Parameter 136 Maximum Offset Minimum Offset 137 Fast Model Slow Model Unit
Extended Industrial –E1S, –E1H, –I1S, –I1H –E2L, –E2S, –I2L, –I2S –E3L, –E3S, –I3L, –I3S
Input Delay Chain Setting (IO_IN_DLY_CHN) 63 0 2.012 2.003 4.541 5.241 6.035 ns
Output Delay Chain Setting (IO_OUT_DLY_CHN) 15 0 0.478 0.475 1.088 1.263 1.462 ns
136 You can set this value in the Intel® Quartus® Prime software by selecting Input Delay Chain Setting or Output Delay Chain Setting in the Assignment Name column.
137 Minimum offset does not include the intrinsic delay.

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