Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
Public
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I2C Timing Characteristics

Table 73.  I2C Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Standard Mode Fast Mode Unit
Min Max Min Max
Tclk Serial clock (SCL) clock period 10 2.5 μs
tHIGH 102 SCL high period 4 103 0.6 104 μs
tLOW 105 SCL low period 4.7 106 1.3 107 μs
tSU;DAT Setup time for serial data line (SDA) data to SCL 0.25 0.1 μs
tHD;DAT 108 Hold time for SCL to SDA data 0 3.15 0 0.6 μs
tVD;DAT and tVD;ACK 109 SCL to SDA output data delay 3.45 110 0.9 111 μs
tSU;STA Setup time for a repeated start condition 4.7 0.6 μs
tHD;STA Hold time for a repeated start condition 4 0.6 μs
tSU;STO Setup time for a stop condition 4 0.6 μs
tBUF SDA high pulse duration between STOP and START 4.7 1.3 μs
tr 112 SCL rise time 1000 20 300 ns
tf 112 SCL fall time 300 20 × (Vdd / 5.5) 113 300 ns
tr 112 SDA rise time 1000 20 300 ns
tf 112 SDA fall time 300 20 × (Vdd / 5.5) 113 300 ns
Figure 16. I2C Timing Diagram
102 You can adjust Tclkhigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
103 The recommended minimum setting for ic_ss_scl_hcnt is 440.
104 The recommended minimum setting for ic_fs_scl_hcnt is 71.
105 You can adjust Tclklow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
106 The recommended minimum setting for ic_ss_scl_lcnt is 500.
107 The recommended minimum setting for ic_fs_scl_lcnt is 141.
108 THD;DAT is affected by the rise and fall time.
109 tVD;DAT and tVD;ACK is affected by the rise and fall time, in addition to the SDA hold time that is set by adjusting the ic_sda_hold register.
110 Use maximum SDA_HOLD = 240 to be within the specification.
111 Use maximum SDA_HOLD = 60 to be within the specification.
112 Rise and fall time parameters vary depending on the external factors such as: characteristics of IO driver, pull-out resistor value, and total capacitance on the transmission line.
113 Vdd is the I2C bus voltage.

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