Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Datasheet
Intel® Arria® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Arria® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications HPS Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Arria® 10 GX/SX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GX/SX Devices Transceiver Performance for Intel® Arria® 10 GT Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Arria® 10 GT Devices Transceiver Specifications for Intel® Arria® 10 GX, SX, and GT Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
HPS Specifications x
HPS Reset Input Requirements HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB ULPI Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Trace Timing Characteristics GPIO Interface
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance HPS PLL Output Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Arria® 10 Device Datasheet

I2C Timing Characteristics

Table 73.  I2C Timing Requirements for Intel® Arria® 10 Devices
Symbol Description Standard Mode Fast Mode Unit
Min Max Min Max
Tclk Serial clock (SCL) clock period 10 — 2.5 — μs
tHIGH 102 SCL high period 4 103 — 0.6 104 — μs
tLOW 105 SCL low period 4.7 106 — 1.3 107 — μs
tSU;DAT Setup time for serial data line (SDA) data to SCL 0.25 — 0.1 — μs
tHD;DAT 108 Hold time for SCL to SDA data 0 3.15 0 0.6 μs
tVD;DAT and tVD;ACK 109 SCL to SDA output data delay — 3.45 110 — 0.9 111 μs
tSU;STA Setup time for a repeated start condition 4.7 — 0.6 — μs
tHD;STA Hold time for a repeated start condition 4 — 0.6 — μs
tSU;STO Setup time for a stop condition 4 — 0.6 — μs
tBUF SDA high pulse duration between STOP and START 4.7 — 1.3 — μs
tr 112 SCL rise time — 1000 20 300 ns
tf 112 SCL fall time — 300 20 × (Vdd / 5.5) 113 300 ns
tr 112 SDA rise time — 1000 20 300 ns
tf 112 SDA fall time — 300 20 × (Vdd / 5.5) 113 300 ns
Figure 16. I2C Timing Diagram
102 You can adjust Tclkhigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
103 The recommended minimum setting for ic_ss_scl_hcnt is 440.
104 The recommended minimum setting for ic_fs_scl_hcnt is 71.
105 You can adjust Tclklow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
106 The recommended minimum setting for ic_ss_scl_lcnt is 500.
107 The recommended minimum setting for ic_fs_scl_lcnt is 141.
108 THD;DAT is affected by the rise and fall time.
109 tVD;DAT and tVD;ACK is affected by the rise and fall time, in addition to the SDA hold time that is set by adjusting the ic_sda_hold register.
110 Use maximum SDA_HOLD = 240 to be within the specification.
111 Use maximum SDA_HOLD = 60 to be within the specification.
112 Rise and fall time parameters vary depending on the external factors such as: characteristics of IO driver, pull-out resistor value, and total capacitance on the transmission line.
113 Vdd is the I2C bus voltage.
Level Two Title