Intel® Arria® 10 Device Datasheet

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ID 683771
Date 2/14/2022
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Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 42.  Memory Block Performance Specifications for Intel® Arria® 10 Devices (VCC and VCCP at 0.9 V Typical Value)
Memory Mode Performance
–E1S, –E1H –I1S, –I1H –E2L, –E2S, –I2L, –I2S –E3S, –E3V –I3S, –I3V Unit
MLAB Single port, all supported widths (×16/×32) 700 660 570 490 490 MHz
Simple dual-port, all supported widths (×16/×32) 700 660 570 490 490 MHz
Simple dual-port with the read-during-write option set to Old Data, all supported widths 460 450 400 330 330 MHz
ROM, all supported width (×16/×32) 700 660 570 490 490 MHz
M20K Block Single-port, all supported widths 730 690 625 530 510 MHz
Simple dual-port, all supported widths 730 690 625 530 510 MHz
Simple dual-port with the read-during-write option set to Old Data, all supported widths 550 520 470 410 410 MHz
Simple dual-port with ECC enabled, 512 × 32 470 450 410 360 360 MHz
Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32 620 590 520 470 470 MHz
True dual port, all supported widths 730 690 600 480 480 MHz
ROM, all supported widths 730 690 625 530 510 MHz
Table 43.  Memory Block Performance Specifications for Intel® Arria® 10 Devices (VCC and VCCP at 0.95 V Typical Value)
Memory Mode Performance
–I1S, –I1H –I2L, –I2S Unit
MLAB Single port, all supported widths (×16/×32) 706 610 MHz
Simple dual-port, all supported widths (×16/×32) 706 610 MHz
Simple dual-port with read and write at the same address 482 428 MHz
ROM, all supported width (×16/×32) 706 610 MHz
M20K Block Single-port, all supported widths 735 670 MHz
Simple dual-port, all supported widths 735 670 MHz
Simple dual-port with the read-during-write option set to Old Data, all supported widths 555 500 MHz
Simple dual-port with ECC enabled, 512 × 32 480 440 MHz
Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32 630 555 MHz
True dual port, all supported widths 735 640 MHz
ROM, all supported widths 735 670 MHz

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