Visible to Intel only — GUID: mcn1413182219187
Ixiasoft
Visible to Intel only — GUID: mcn1413182219187
Ixiasoft
High-Speed I/O Specifications
Symbol | Condition | –E1S 72, –E1H, –I1S72, –I1H | –E2L, –E2S72, –I2L, –I2S72 | –E3L, –E3S72, –E3V, –I3L, –I3S72, –I3V | Unit | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK_in (input clock frequency) True Differential I/O Standards | Clock boost factor W = 1 to 40 73 | 10 | — | 800 | 10 | — | 700 | 10 | — | 625 | MHz | |
fHSCLK_in (input clock frequency) Single Ended I/O Standards | Clock boost factor W = 1 to 40 73 | 10 | — | 625 | 10 | — | 625 | 10 | — | 525 | MHz | |
fHSCLK_OUT (output clock frequency) | — | — | — | 800 74 | — | — | 700 74 | — | — | 625 74 | MHz | |
Transmitter | True Differential I/O Standards - fHSDR (data rate) 75 | SERDES factor J = 4 to 10 76 77 78 | 78 | — | 1600 | 78 | — | 1434 | 78 | — | 1250 | Mbps |
SERDES factor J = 3 76 77 78 | 78 | — | 1200 | 78 | — | 1076 | 78 | — | 938 | Mbps | ||
SERDES factor J = 2, uses DDR registers | 78 | — | 333 79 | 78 | — | 275 79 | 78 | — | 250 79 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 78 | — | 333 79 | 78 | — | 275 79 | 78 | — | 250 79 | Mbps | ||
tx Jitter - True Differential I/O Standards | Total jitter for data rate, 600 Mbps – 1.6 Gbps | — | — | 160 | — | — | 200 | — | — | 250 | ps | |
Total jitter for data rate, < 600 Mbps | — | — | 0.1 | — | — | 0.12 | — | — | 0.15 | UI | ||
tDUTY 80 | TX output clock duty cycle for Differential I/O Standards | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | % | |
tRISE & & tFALL 77 81 | True Differential I/O Standards | — | — | 160 | — | — | 180 | — | — | 200 | ps | |
TCCS 80 75 | True Differential I/O Standards | — | — | 150 | — | — | 150 | — | — | 150 | ps | |
Receiver | True Differential I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 to 10 76 77 78 | 150 | — | 1600 | 150 | — | 1434 | 150 | — | 1250 | Mbps |
SERDES factor J = 3 76 77 78 | 150 | — | 1200 | 150 | — | 1076 | 150 | — | 938 | Mbps | ||
fHSDR (data rate) (without DPA) 75 | SERDES factor J = 3 to 10 | 78 | — | 82 | 78 | — | 82 | 78 | — | 82 | Mbps | |
SERDES factor J = 2, uses DDR registers | 78 | — | 79 | 78 | — | 79 | 78 | — | 79 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 78 | — | 79 | 78 | — | 79 | 78 | — | 79 | Mbps | ||
DPA (FIFO mode) | DPA run length | — | — | — | 10000 | — | — | 10000 | — | — | 10000 | UI |
DPA (soft CDR mode) | DPA run length | SGMII/GbE protocol | — | — | 5 | — | — | 5 | — | — | 5 | UI |
All other protocols | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | ||
Soft CDR mode | Soft-CDR ppm tolerance | — | — | — | 300 | — | — | 300 | — | — | 300 | ± ppm |
Non DPA mode | Sampling Window | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
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